Texas Instruments LMH0056SQE/NOPB
- Part No.:
- LMH0056SQE/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Video Processing
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
LMH0056SQE/NOPB.pdf
- Description:
- IC VIDEO RECLOCKER 48WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LMH0056SQE/NOPB from Texas Instruments is an HD/SD SDI reclocker with integrated 4:1 input multiplexer, designed for serial digital video retiming at 143 Mbps, 270 Mbps, 1.483 Gbps, and 1.485 Gbps. It supports SMPTE 259M (A & C) and SMPTE 292M standards, delivers two differential LVPECL-compatible outputs, and operates from a single 3.3V supply in industrial temperature range (−40°C to +85°C). It is used in digital video routers, format converters, and DVB-ASI equipment.
For engineers reviewing the LMH0056SQE/NOPB datasheet, LMH0056SQE/NOPB pinout, LMH0056SQE/NOPB application, or LMH0056SQE/NOPB equivalent, key selection considerations include its auto-rate detection capability, dual-output flexibility (data or data-rate clock), 48-pin WQFN package with exposed thermal pad, jitter suppression performance (<0.1 UIP-P output jitter at 1.485 Gbps), and LVCMOS control interface compatibility.
Technical Context
The LMH0056SQE/NOPB implements a PLL-based reclocking architecture with automatic data rate detection across four standard SDI/HD-SDI rates. Its VCO and loop filters (LF1/LF2) are optimized for low-jitter recovery at both SD (270 Mbps) and HD (1.485 Gbps) frequencies, with loop bandwidths of 300 kHz (270 Mbps) and 2.0 MHz (1485 Mbps).
It integrates a 4:1 differential multiplexer controlled by SEL0/SEL1, dual CML/LVPECL outputs (SDO and configurable SCO/SDO2), and LVCMOS logic I/O including RATE0/RATE1, SCO_EN, LOCK DETECT, and SD/HD indicator. The device accepts a 27 MHz crystal or external reference and supports both auto-bypass and manual bypass modes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rates | 143 Mbps, 270 Mbps, 1.483 Gbps, 1.485 Gbps - supports SMPTE 259M (A/C) and SMPTE 292M compliant video streams |
| Input Jitter Tolerance | >6 UIP-P at 143/270 Mbps - enables robust locking to degraded SDI signals with high accumulated jitter |
| Output Jitter | 0.05–0.1 UIP-P at 1.483/1.485 Gbps - ensures clean retimed data for downstream cable drivers or deserializers |
| Supply Voltage | 3.3 V ±5% - single-rail operation simplifies power design and reduces BOM count |
| Power Consumption | 360 mW typical - enables thermal management in dense video routing PCB layouts |
| Operating Temperature | −40°C to +85°C - qualified for industrial-grade broadcast and professional AV equipment |
| Differential Output Level | 800 mVP-P ±10% into 100 Ω - matches standard LVPECL/CML termination for interoperability with TI's LMH0002, LMH0031, etc. |
Pinout & Package
LMH0056SQE/NOPB is housed in a 48-pin WQFN package (RHS0048A) with an exposed die attach pad (DAP) electrically connected to VEE (ground). The package features 0.5 mm pitch, 7.15 × 7.15 mm body size, and 0.8 mm max height. Thermal pad soldering is mandatory for mechanical stability and thermal performance.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SDI0–SDI3 (pins 1–2, 4–5, 7–8, 10–11) | Differential serial data inputs | Four independent CML/LVPECL-compatible inputs; selected via SEL0/SEL1 for 4:1 multiplexing |
| SDO (pins 32–33) | Primary retimed differential data output | Always active retimed output; drives 100 Ω differentially terminated loads |
| SCO/SDO2 (pins 28–29) | Configurable secondary output | Selectable via SCO_EN: second retimed data (low) or low-jitter data-rate clock (high) |
| XTAL IN/EXT CLK (pin 18), XTAL OUT (pin 22) | 27 MHz reference interface | Accepts parallel-resonant crystal (20 pF load) or LVCMOS 27 MHz clock; ±50 ppm tolerance supported |
| SEL0/SEL1 (pins 47–48), RATE0/RATE1 (pins 45–46) | LVCMOS control inputs | Set input channel (00–11) and operating mode (auto-detect, 270 Mbps, or 1.485 Gbps) |
| LOCK DET (pin 24), SD/HD (pin 36) | LVCMOS status indicators | LOCK DET = high when PLL locked; SD/HD = high for SD rates (143/270 Mbps), low for HD (1.485 Gbps) |
| O/P MUTE (pin 16), BYPASS/AUTOBYPASS (pin 15) | LVCMOS functional controls | MUTE = active-low output disable; BYPASS = high forces transparent path, low enables auto-bypass on unlock |
Key Features
| Feature | Design Value |
|---|---|
| Auto-rate detection with acquisition time ≤16 ms | Enables plug-and-play integration in multi-standard video systems without manual configuration |
| Configurable SCO/SDO2 output | Eliminates need for external clock buffer when generating synchronized data-rate clocks for downstream devices |
| Integrated 4:1 multiplexer with LVCMOS select | Reduces system-level component count versus discrete mux + reclocker solutions |
| Dual differential LVPECL-compatible outputs | Supports redundant signal distribution or simultaneous feeding of cable driver and deserializer paths |
| Industrial temperature range and 8 kV HBM ESD rating | Ensures reliability in broadcast infrastructure environments with variable thermal and handling conditions |
Applications
| Digital Video Routers | Video Format Converters |
|---|---|
Use Scenario: Receiving and redistributing multiple SD/HD-SDI feeds from cameras, recorders, or switchers within a broadcast facility. IC Role / Device Role / Timing Role: Reclocker with 4:1 input multiplexer that cleans jitter from incoming SDI streams and provides two synchronized outputs per selected source. Use Value: Enables stable signal distribution over long coaxial runs by suppressing accumulated jitter up to 1.485 Gbps, meeting SMPTE 292M compliance requirements. |
Use Scenario: Converting between SD-SDI (270 Mbps) and HD-SDI (1.485 Gbps) formats in real-time production systems. IC Role / Device Role / Timing Role: Rate-adaptive reclocker that detects incoming data rate and re-times it with minimal latency and jitter. Use Value: Maintains signal integrity during format transitions; SD/HD output pin provides direct rate indication for downstream logic control. |
| DVB-ASI Equipment | Professional Video Editing Systems |
Use Scenario: Retiming MPEG-2 transport streams carried over DVB-ASI physical layer at 270 Mbps in satellite or terrestrial broadcast headends. IC Role / Device Role / Timing Role: SDI reclocker configured for 270 Mbps operation, supporting DVB-ASI without harmonic lock issues. Use Value: Ensures bit-accurate regeneration of ASI streams, preventing packet loss due to timing violations in demodulator or decoder interfaces. |
Use Scenario: Synchronizing multiple video processing stages (e.g., color correction, keying, compositing) requiring low-jitter reference clocks and clean data paths. IC Role / Device Role / Timing Role: Dual-output reclocker providing one retimed data stream and one aligned data-rate clock for timing-critical subsystems. Use Value: Reduces inter-stage skew and improves frame alignment accuracy; SCO_EN allows dynamic clock/data routing without hardware changes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SDI reclocking applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH0044SQE/NOPB | Single-input SDI equalizer (not reclocker); no PLL, no jitter cleanup, no multiplexer | Used for signal conditioning only-requires separate reclocker stage for jitter reduction | Select LMH0044SQE/NOPB only when input signal integrity is poor but reclocking is handled elsewhere |
| LMH0384MA/NOPB | Quad-channel SDI reclocker with integrated cable driver; higher power (1.2 W), larger 64-pin HTSSOP package | Targets high-density routing cards needing four independent reclocked outputs per chip | Choose LMH0384MA/NOPB for multi-channel fanout; LMH0056SQE/NOPB remains optimal for 4:1 mux + dual-output compact designs |
Compared with LMH0044SQE/NOPB and LMH0384MA/NOPB, the LMH0056SQE/NOPB uniquely combines input multiplexing, auto-rate detection, and dual-output flexibility in a thermally efficient 48-pin WQFN-making it the preferred solution for space-constrained, multi-source SDI retiming nodes where jitter suppression and signal routing intelligence are co-located.
Availability
LMH0056SQE/NOPB is available at Aetrix Electronics and suitable for digital video routers, broadcast infrastructure equipment, and professional video editing systems requiring stable component supply across extended product lifecycles.
Supply support for LMH0056SQE/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in broadcast video signal conditioning ICs.
The LMH0056SQE/NOPB belongs to TI's LMH high-speed video interface product line, engineered specifically for SMPTE-compliant SDI/HD-SDI signal integrity restoration in professional broadcast, post-production, and distribution systems.
FAQ
What video standards does the LMH0056SQE/NOPB support?
The LMH0056SQE/NOPB supports SMPTE 259M (A & C) for SD-SDI at 143 Mbps and 270 Mbps, and SMPTE 292M for HD-SDI at 1.483 Gbps and 1.485 Gbps. It also supports DVB-ASI operation at 270 Mbps. All supported standards are explicitly confirmed in the official SNLS236C datasheet, and the device performs automatic rate detection and jitter suppression per each standard's timing requirements.
How does the LMH0056SQE/NOPB handle input multiplexing and output configuration?
The LMH0056SQE/NOPB uses SEL0 and SEL1 pins to select one of four differential inputs (SDI0–SDI3) for retiming. Its SCO/SDO2 output (pins 28–29) is configurable via SCO_EN: when low, it delivers a second retimed data stream; when high, it outputs a low-jitter data-rate clock aligned to the active data stream. This dual-mode capability is hardware-controlled and requires no firmware or external logic.
What is the function of the SD/HD pin on the LMH0056SQE/NOPB?
The SD/HD pin (pin 36) is an LVCMOS indicator output that signals whether the LMH0056SQE/NOPB is locked to an SD rate (143 or 270 Mbps, output = high) or HD rate (1.483 or 1.485 Gbps, output = low). It is registered and valid only when LOCK DETECT is asserted; otherwise, it defaults to HD (low). This pin enables real-time rate-aware control of downstream components like cable drivers.
Does the LMH0056SQE/NOPB require external loop filter components?
Yes, the LMH0056SQE/NOPB requires two external passive loop filter components: LF1 (pin 43) and LF2 (pin 44). These connect to the internal PLL and must be populated per the values specified in the SNLS236C datasheet's "Loop Filter Design" section to ensure stable lock and optimal jitter performance at target data rates (e.g., 300 kHz bandwidth for 270 Mbps, 2.0 MHz for 1.485 Gbps).
What is the recommended power supply decoupling for the LMH0056SQE/NOPB?
The LMH0056SQE/NOPB requires local 3.3 V supply decoupling using a 100 nF ceramic capacitor placed near each VCC pin (pins 3, 6, 9, 12, 14, 30, 31, 34, 35), plus a bulk 4.7 µF tantalum or ceramic capacitor near the package. All VEE pins (13, 17, 19–21, 23–27, 38–42) must be solidly connected to ground, and the exposed die attach pad (DAP) must be soldered to the PCB ground plane for thermal and electrical integrity.
LMH0056SQE/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Reclocker
- Applications:
- Professional Video
- Standards:
- DVB-ASI, SMPTE
- Control Interface:
- Serial
- Voltage - Supply:
- 3.135V ~ 3.465V
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 48-WQFN (7x7)
LMH0056SQE/NOPB FAQ
1.How can I place an order for LMH0056SQE/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH0056SQE/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH0056SQE/NOPB reliable?
The price and inventory of LMH0056SQE/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH0056SQE/NOPB is usually 5 days.
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We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMH0056SQE/NOPB transactions.
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LMH0056SQE/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMH0056SQE/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH0056SQE/NOPB?
For technical support, including LMH0056SQE/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH0056SQE/NOPB requirements.
6.How does Aetrix verify that LMH0056SQE/NOPB is sourced from the original manufacturer or authorized distributors?
All LMH0056SQE/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH0056SQE/NOPB meets industry standards.
7.What is the process for return or replacement of LMH0056SQE/NOPB?
All LMH0056SQE/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMH0056SQE/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH0056SQE/NOPB part is unused and in its original packaging.
Return procedure for LMH0056SQE/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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