Texas Instruments LMH0070SQE/NOPB
- Part No.:
- LMH0070SQE/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
LMH0070SQE/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 48WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,475
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Product details
Overview
LMH0070SQE/NOPB from Texas Instruments is a 270 Mbps SDI serializer and integrated SMPTE-compliant cable driver with LVDS interface, SMBus configuration, and on-chip TXCLK PLL for clock noise reduction. It supports SMPTE 259M-C (SD), SMPTE 292M (HD), and DVB-ASI standards, and operates in industrial temperature range (−40°C to +85°C) with 440 mW typical power dissipation.
For engineers reviewing the LMH0070SQE/NOPB datasheet, LMH0070SQE/NOPB pinout, LMH0070SQE/NOPB application, or LMH0070SQE/NOPB equivalent, this device serves as a low-power, FPGA-attach serial digital interface solution requiring precise SDI output amplitude control (via RSET), LVDS timing compliance, and configurable DVB_ASI mode for broadcast video infrastructure.
Technical Context
The LMH0070SQE/NOPB implements a parallel-to-serial 5:1 conversion using DDR LVDS inputs (TX[4:0]±, TXCLK±) and generates a CML-compatible SDI output (TXOUT±) compliant with SMPTE 259M-C at 270 Mbps. Its internal PLL locks to the LVDS input clock without external VCO or reference crystal.
Configuration is performed via 3.3V SMBus (SCK/SDA/SMB_CS), supporting register-level control of DVB_ASI mode, GPIO[2:0], LOCK status, and reset. The device uses an external RSET resistor (nominally 8.06 kΩ) to set output amplitude to 800 mV into 75 Ω, and requires external loop filter components (LF_REF/LF_CP) for PLL stability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Standard Support | SMPTE 259M-C (SD), SMPTE 292M (HD), DVB-ASI - ensures interoperability with broadcast-grade SD/HD video equipment |
| Data Rate | 270 Mbps - fixed rate per datasheet Table 1; no support for 1.485 Gbps or 2.97 Gbps modes |
| Output Amplitude | 720–880 mV into 75 Ω - adjustable via RSET pin; 800 mV nominal for SMPTE compliance |
| Input Interface | 5-bit DDR LVDS (TX[4:0]±, TXCLK±) with 100 Ω internal termination - matches FPGA LVDS I/O without external resistors |
| Power Supply | VDD3V3 = 3.135–3.465 V; VDD2V5 = 2.375–2.625 V - dual-rail operation with dedicated PLL supply (VDDPLL) |
| Output Jitter | 100–200 ps peak-to-peak at 270 Mbps - measured per SMPTE RP184; impacts eye diagram integrity over coax |
| Operating Temperature | −40°C to +85°C - qualified for industrial video capture and distribution systems |
Pinout & Package
LMH0070SQE/NOPB is housed in a 48-pin WQFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad (DAP = GND). Pin assignment follows TI SNLS271I Rev. April 2013.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TX[4:0]± | LVDS data input pair | 5-channel DDR LVDS bus; internal 100 Ω termination enables direct FPGA connection without external resistors |
| TXCLK± | LVDS clock input pair | DDR clock reference for serialization; determines 270 Mbps output rate; internal termination applied |
| TXOUT± | CML serial output | Differential SDI output compliant with SMPTE 259M-C; requires external 75 Ω back-termination to 2.5 V |
| RSET | Analog amplitude control | Resistor-to-ground sets output swing; 8.06 kΩ yields 800 mV nominal into 75 Ω load |
| SMB_CS, SCK, SDA | SMBus interface | 3.3V LVCMOS-configurable control bus; supports multi-drop via chip select; not 5V tolerant |
| LOCK | PLL lock indicator | LVCMOS output; low = PLL locked to TXCLK; used for system readiness monitoring |
| RESET | Asynchronous reset | Active-low LVCMOS input; forces register reset and PLL reacquisition when asserted |
| DVB_ASI | Mode select input | LVCMOS input; high enables DVB-ASI 8b10b encoding using TX4 as data valid; low enables standard SDI mode |
Key Features
| Feature | Design Value |
|---|---|
| Integrated SMPTE cable driver | Meets SMPTE 259M-C output amplitude, rise/fall time, and return loss specs without external driver IC |
| Bypassable 8b10b encoding | Configurable via DVB_ASI pin; enables DVB-ASI transport stream compatibility while retaining SDI baseband mode |
| No external VCO or clock reference required | On-chip PLL synthesizes serial clock directly from LVDS TXCLK input - eliminates BOM cost and layout complexity |
| Industrial temperature range | −40°C to +85°C operation validated - suitable for DVRs, video switchers, and field-deployed camera systems |
| Small 48-pin WQFN package | 7 mm × 7 mm footprint with exposed DAP - enables high-density PCB layouts in space-constrained video modules |
Applications
| Video Cameras | DVRs |
|---|---|
Use Scenario: HD/SD video capture in professional broadcast cameras with FPGA-based image processing pipeline. IC Role / Device Role / Timing Role: Serializer converts parallel LVDS pixel data from FPGA to SMPTE 259M-C-compliant SDI output for coax transmission. Use Value: Integrated cable driver ensures SMPTE-compliant 800 mV output swing and <200 ps jitter at 270 Mbps, enabling reliable 100+ meter coax runs. |
Use Scenario: Digital video recorder front-end accepting SD/HD baseband video from multiple sources. IC Role / Device Role / Timing Role: SDI serializer interfaces FPGA video buffer to coax output stage; DVB_ASI mode supports ASI transport stream ingestion. Use Value: SMBus configurability allows runtime switching between SDI and DVB-ASI modes without hardware change - simplifies multi-standard DVR design. |
| Video Switchers | Video Editing Systems |
Use Scenario: Real-time routing of SD/HD video signals in production switchers with FPGA-controlled signal path selection. IC Role / Device Role / Timing Role: Serializer formats FPGA-processed video for SMPTE 259M-C output; LOCK pin provides PLL lock status for system synchronization. Use Value: 270 Mbps fixed-rate operation and −40°C to +85°C rating ensure deterministic latency and reliability in live broadcast environments. |
Use Scenario: High-fidelity video ingest path in non-linear editing workstations handling SD/HD material. IC Role / Device Role / Timing Role: Converts parallel LVDS video data from frame grabber FPGA to robust SDI output for monitor feed or archive interface. Use Value: Internal 100 Ω LVDS termination and controlled-output impedance minimize signal integrity issues across long PCB traces to connectors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SDI serializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH0040SQE/NOPB | Supports 270 Mbps and 1.485 Gbps; wider data rate range; identical pinout and package | Required for HD-SDI (1.485 Gbps) applications; not limited to SD-only use case | Select LMH0040SQE/NOPB when HD-SDI capability or future upgrade path to 1.485 Gbps is needed. |
| LMH0340SQE/NOPB | Supports 270 Mbps, 1.485 Gbps, and 2.97 Gbps; full 3G-SDI compliance; same WQFN-48 package | Enables 3G-SDI transmission; includes enhanced output drive strength and jitter performance for longer cable runs | Choose LMH0340SQE/NOPB for 3G-SDI infrastructure where backward compatibility with SD/HD is mandatory. |
Compared with LMH0070SQE/NOPB, LMH0040SQE/NOPB adds 1.485 Gbps HD-SDI support while maintaining SD compatibility, and LMH0340SQE/NOPB extends to 2.97 Gbps 3G-SDI - both retain identical pinout and SMBus register map, enabling scalable design reuse across SD/HD/3G platforms.
Availability
LMH0070SQE/NOPB is available at Aetrix Electronics and suitable for video cameras, DVRs, video switchers, and video editing systems requiring stable component supply, SMPTE 259M-C compliance, and industrial-temperature operation.
Supply support for LMH0070SQE/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with broad industrial and automotive portfolio coverage.
The LMH0070SQE/NOPB belongs to TI's FPGA-Attach SER/DES product line, designed specifically for low-latency, standards-compliant serial digital video interfacing between FPGAs and coaxial SDI infrastructure.
FAQ
What video standards does the LMH0070SQE/NOPB support?
The LMH0070SQE/NOPB supports SMPTE 259M-C (SD-SDI), SMPTE 292M (HD-SDI), and DVB-ASI standards. It operates exclusively at 270 Mbps per datasheet Table 1 and does not support 1.485 Gbps or 2.97 Gbps rates. Its output meets SMPTE 259M-C amplitude, jitter, and return loss requirements when configured with nominal RSET and proper termination.
Does the LMH0070SQE/NOPB require an external clock source or VCO?
No, the LMH0070SQE/NOPB does not require an external VCO or clock reference. It uses an integrated TXCLK PLL that locks directly to the LVDS input clock (TXCLK±) provided by the host FPGA. This eliminates external timing components and reduces board area and BOM cost while maintaining SMPTE-compliant jitter performance at 270 Mbps.
How is output amplitude controlled on the LMH0070SQE/NOPB?
Output amplitude on the LMH0070SQE/NOPB is controlled via the RSET pin: a resistor from RSET to GND sets the output swing. A nominal 8.06 kΩ resistor yields 800 mV into a 75 Ω load, meeting SMPTE 259M-C requirements. The relationship is monotonic and documented in Figure 8 of the datasheet; values outside 6–12 kΩ may compromise compliance.
Can the LMH0070SQE/NOPB operate in DVB-ASI mode?
Yes, the LMH0070SQE/NOPB supports DVB-ASI mode when the DVB_ASI pin is driven high. In this mode, TX4± acts as a data valid signal, and TX0–TX3 form nibbles for 8b10b encoding before serialization. When DVB_ASI is low, the device operates in standard SDI mode. Both modes use the same TXOUT± output pins and SMPTE-compliant driver.
What is the recommended power supply sequencing for the LMH0070SQE/NOPB?
The LMH0070SQE/NOPB requires 3.3 V (VDD3V3) and 2.5 V (VDD2V5) supplies. TI specifies that VDD3V3 must be powered before VDD2V5, though timing between ramps is not critical. A 22 μF capacitor is mandatory on VDDPLL (3.3 V rail), and each power pin requires local 0.1 μF + 4.7 μF bypassing. The exposed DAP pad must be soldered to solid GND plane.
LMH0070SQE/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Displays
- Interface:
- SMBus (2-Wire/I2C)
- Voltage - Supply:
- 3.135V ~ 3.465V
- Supplier Device Package:
- 48-WQFN (7x7)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LMH0070SQE/NOPB FAQ
1.How can I place an order for LMH0070SQE/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH0070SQE/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH0070SQE/NOPB reliable?
The price and inventory of LMH0070SQE/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH0070SQE/NOPB is usually 5 days.
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Once your LMH0070SQE/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH0070SQE/NOPB?
For technical support, including LMH0070SQE/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH0070SQE/NOPB requirements.
6.How does Aetrix verify that LMH0070SQE/NOPB is sourced from the original manufacturer or authorized distributors?
All LMH0070SQE/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH0070SQE/NOPB meets industry standards.
7.What is the process for return or replacement of LMH0070SQE/NOPB?
All LMH0070SQE/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMH0070SQE/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH0070SQE/NOPB part is unused and in its original packaging.
Return procedure for LMH0070SQE/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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