Texas Instruments LMH0070SQ/NOPB
- Part No.:
- LMH0070SQ/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 48-WFQFN Exposed Pad
- Datasheet:
-
LMH0070SQ/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 48WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LMH0070SQ/NOPB from Texas Instruments is a 270 Mbps SMPTE 259M-C–compliant SDI serializer and cable driver with LVDS interface, integrated TXCLK PLL for clock noise reduction, 3.3V SMBus configuration, and 48-pin WQFN package. It converts parallel 5-bit LVDS video data into serial SDI output compliant with broadcast video standards for camera-to-switcher links.
For engineers reviewing the LMH0070SQ/NOPB datasheet, LMH0070SQ/NOPB pinout, LMH0070SQ/NOPB application, or LMH0070SQ/NOPB equivalent, this device supports DVB-ASI mode selection via GPIO, programmable output amplitude via RSET, and lock status monitoring - critical for broadcast-grade video signal integrity validation and FPGA-attached SER/DES system integration.
Technical Context
The LMH0070SQ/NOPB implements a parallel-to-serial 5:1 conversion architecture with integrated 8b10b encoding in DVB-ASI mode, using an internal PLL to generate the serialization clock from the LVDS TXCLK input (26.5–28 MHz). Its CML-based TXOUT+/- output drives 75 Ω coaxial cable directly with programmable amplitude (720–880 mV) and controlled rise/fall times (400–1000 ps).
Configuration occurs over a 3.3V SMBus interface (10–100 kHz) with chip-select (SMB_CS), clock (SCK), and bidirectional data (SDA) pins; control logic includes RESET (LVCMOS active-low), LOCK (open-drain status), and DVB_ASI mode select - enabling dynamic switching between SDI and DVB-ASI protocols without FPGA reconfiguration.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Standard | SMPTE 259M-C compliant (SD); supports DVB-ASI mode via DVB_ASI pin |
| Data Rate | 270 Mbps fixed - matches NTSC/PAL SD video bit rate; no HD/3G support |
| Output Amplitude | 720–880 mV into 75 Ω - adjustable via external RSET resistor (nominal 8.06 kΩ) |
| Output Jitter | 100–200 ps peak-to-peak at 270 Mbps - meets SMPTE RP184 for SD video timing stability |
| Power Dissipation | 400–470 mW typical - split across VDD3V3 (73–85 mA) and VDD2V5 (63–69 mA) |
| Operating Temp | −40°C to +85°C - qualified for industrial video equipment environments |
| LVDS Interface | 5-bit DDR TX[4:0]± + TXCLK± - internally terminated at 100 Ω, supports ≤25 cm PCB trace length |
Pinout & Package
LMH0070SQ/NOPB uses a 48-pin WQFN package (7 mm × 7 mm, 0.5 mm pitch) with exposed thermal pad (DAP = GND). Pin mapping is validated per TI SNLS271I Rev. April 2013.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| TX[4:0]± | LVDS data input pair | 5-channel DDR bus accepting parallel video data; internal 100 Ω termination enables direct FPGA connection |
| TXCLK± | LVDS clock input pair | DDR clock reference (26.5–28 MHz); determines serialization timing and PLL lock acquisition |
| TXOUT+/TXOUT− | CML serial output pair | Differential SDI output driving 75 Ω coax; amplitude set by RSET, slew rate auto-adjusted for SD compliance |
| SMB_CS / SCK / SDA | SMBus configuration interface | 3.3V LVCMOS 2-wire bus for register writes (e.g., DVB_ASI mode, RSET calibration, reset control) |
| RESET / LOCK / DVB_ASI | Control & status signals | Active-low hardware reset; open-drain LOCK indicates PLL lock; DVB_ASI pin selects protocol mode (H = DVB-ASI, L = SMPTE) |
| RSET / LF_CP / LF_REF | Analog configuration inputs | RSET sets output amplitude; LF_CP/LF_REF connect external loop filter (500 Ω + 0.1 μF) for PLL stability |
| VDD3V3 / VDD2V5 / VDDPLL / GND | Power supply terminals | Separate 3.3V (I/O, SMBus, PLL core) and 2.5V (LVDS input, output driver) rails; DAP must be soldered to GND for thermal/EMI performance |
Key Features
| Feature | Design Value |
|---|---|
| Bypassable 8b10b encoding | Enabled only in DVB_ASI mode (TX4± as data valid); allows seamless transition between SMPTE and DVB-ASI transport layers |
| Integrated TXCLK PLL | Cleans jitter from FPGA-generated clock source - eliminates need for external VCO or crystal reference |
| Variable output cable driver | Programmable amplitude (720–880 mV) via RSET resistor; meets SMPTE 259M-C output return loss (≥15 dB up to 1485 MHz) |
| LVDS-to-SDI conversion | Direct 5-bit LVDS input → serial SDI output; no external serializer IP required when paired with TI FPGA-Attach reference designs |
| Industrial temperature range | −40°C to +85°C operation - supports deployment in broadcast cameras, field recorders, and mobile production units |
Applications
| Professional Video Camera | SD Broadcast DVR |
|---|---|
Use Scenario: Capturing NTSC/PAL video in ENG/EFP cameras with FPGA-based image processing pipeline. IC Role / Device Role / Timing Role: Serializer converting 5-bit LVDS pixel data from FPGA to SMPTE 259M-C-compliant SDI output for coaxial transmission. Use Value: Eliminates external clock synthesis; 270 Mbps fixed-rate operation ensures deterministic latency and SMPTE-aligned timing for real-time preview and recording. |
Use Scenario: Ingesting SD video streams from multiple sources into a broadcast-grade digital video recorder. IC Role / Device Role / Timing Role: Cable driver ensuring robust SDI signal integrity over long coax runs to recording modules. Use Value: Programmable RSET and integrated loop filter enable precise amplitude and jitter control - critical for error-free recording at baseband SD resolution. |
| Live Production Switcher | Video Editing System I/O |
Use Scenario: Input stage of multi-channel SD video switcher handling feeds from studio cameras and playback servers. IC Role / Device Role / Timing Role: Protocol-aware serializer supporting both SMPTE 259M-C and DVB-ASI modes via DVB_ASI pin. Use Value: Single hardware design accommodates dual-standard workflows; SMBus configuration enables runtime mode switching without FPGA reprogramming. |
Use Scenario: SDI interface card in non-linear editing workstations requiring reliable capture/playback of legacy SD content. IC Role / Device Role / Timing Role: Low-jitter (100–200 ps) serializer maintaining SMPTE RP184 alignment for frame-accurate editing. Use Value: Integrated PLL cleans FPGA clock noise - avoids timing errors during high-speed capture that cause dropped frames or audio sync drift. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SDI serializer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH0040SQ/NOPB | Supports 270 Mbps and 1.485 Gbps (HD-SDI); wider data rate range but same 48-pin WQFN package | Required for HD video systems; not drop-in compatible due to higher max clock frequency (149 MHz vs. 28 MHz) | Select LMH0040SQ/NOPB only when HD-SDI capability is needed; LMH0070SQ/NOPB remains optimal for cost-sensitive SD-only designs. |
| LMH0340SQ/NOPB | Supports 270 Mbps, 1.485 Gbps, and 2.97 Gbps (3G-SDI); includes enhanced cable drive strength and jitter specs | Required for UHD/4K infrastructure; incompatible pin-level timing (TXCLK up to 297 MHz) and higher power (545 mW) | LMH0340SQ/NOPB is over-specified for SD applications; LMH0070SQ/NOPB delivers exact SMPTE 259M-C compliance with lower BOM cost and thermal load. |
Compared with LMH0040SQ/NOPB and LMH0340SQ/NOPB, the LMH0070SQ/NOPB provides strictly SD-optimized performance: fixed 270 Mbps operation, minimal power (470 mW max), and simplified clocking (28 MHz TXCLK), making it the most efficient choice for dedicated NTSC/PAL video systems where HD/3G capability adds unnecessary complexity and cost.
Availability
LMH0070SQ/NOPB is available at Aetrix Electronics and suitable for professional video cameras, SD broadcast DVRs, live production switchers, and video editing system I/O requiring stable component supply across extended product lifecycles.
Supply support for LMH0070SQ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and communications markets.
The LMH0070SQ/NOPB belongs to TI's FPGA-Attach SER/DES product line, designed specifically for low-latency, standards-compliant video serialization in broadcast and professional AV equipment interfacing with FPGAs.
FAQ
What video standards does the LMH0070SQ/NOPB support?
The LMH0070SQ/NOPB supports SMPTE 259M-C for standard-definition (SD) video at 270 Mbps and DVB-ASI mode via the DVB_ASI pin. It does not support SMPTE 292M (HD-SDI) or SMPTE 424M (3G-SDI). Its fixed 270 Mbps data rate aligns precisely with NTSC and PAL baseband video timing, and all electrical characteristics - including output amplitude (720–880 mV), jitter (100–200 ps), and return loss (≥15 dB) - are validated per SMPTE 259M-C requirements.
How is output amplitude configured on the LMH0070SQ/NOPB?
Output amplitude on the LMH0070SQ/NOPB is set by an external resistor connected between the RSET pin and GND. A nominal 8.06 kΩ resistor yields 800 mV into 75 Ω, meeting SMPTE 259M-C specification. The relationship is monotonic: decreasing RSET lowers amplitude, increasing RSET raises it - verified across 720–880 mV in TI characterization. This analog trim replaces digital register writes, simplifying layout and reducing configuration overhead compared to alternatives requiring SMBus calibration.
Does the LMH0070SQ/NOPB require an external clock source?
No, the LMH0070SQ/NOPB does not require an external VCO or crystal oscillator. It uses an integrated PLL that locks to the LVDS TXCLK± input (26.5–28 MHz), cleaning jitter from the FPGA-provided clock. External components are limited to a loop filter (500 Ω + 0.1 μF) on LF_CP/LF_REF pins and a 22 μF capacitor on VDDPLL. This eliminates BOM cost and board space associated with discrete clock generation, while maintaining SMPTE RP184 jitter compliance at 270 Mbps.
What is the function of the DVB_ASI pin on the LMH0070SQ/NOPB?
The DVB_ASI pin on the LMH0070SQ/NOPB is a mode-select input that configures the device for either SMPTE 259M-C (L) or DVB-ASI (H) operation. When high, TX4± becomes a data-valid signal, and the internal 8b10b encoder processes nibbles from TX0–TX3 into 10-bit symbols for ASI transport. When low, the device operates in standard SMPTE mode, serializing all five LVDS lanes. This pin enables hardware-level protocol switching without SMBus register writes or FPGA firmware changes.
Can the LMH0070SQ/NOPB be used in HD-SDI systems?
No, the LMH0070SQ/NOPB is not suitable for HD-SDI systems. Its maximum supported data rate is 270 Mbps, matching SMPTE 259M-C for SD video only. HD-SDI requires 1.485 Gbps (SMPTE 292M), which the LMH0070SQ/NOPB does not support - its TXCLK input is rated only up to 28 MHz, and its output driver is characterized solely for SD compliance (e.g., 100–200 ps jitter at 270 Mbps). For HD-SDI, TI recommends LMH0040SQ/NOPB or LMH0340SQ/NOPB instead.
LMH0070SQ/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 48-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Displays
- Interface:
- SMBus (2-Wire/I2C)
- Voltage - Supply:
- 3.135V ~ 3.465V
- Supplier Device Package:
- 48-WQFN (7x7)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LMH0070SQ/NOPB FAQ
1.How can I place an order for LMH0070SQ/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH0070SQ/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH0070SQ/NOPB reliable?
The price and inventory of LMH0070SQ/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH0070SQ/NOPB is usually 5 days.
3.What payment methods are accepted for LMH0070SQ/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMH0070SQ/NOPB transactions.
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4.How is shipping managed for LMH0070SQ/NOPB?
LMH0070SQ/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMH0070SQ/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH0070SQ/NOPB?
For technical support, including LMH0070SQ/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH0070SQ/NOPB requirements.
6.How does Aetrix verify that LMH0070SQ/NOPB is sourced from the original manufacturer or authorized distributors?
All LMH0070SQ/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH0070SQ/NOPB meets industry standards.
7.What is the process for return or replacement of LMH0070SQ/NOPB?
All LMH0070SQ/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMH0070SQ/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH0070SQ/NOPB part is unused and in its original packaging.
Return procedure for LMH0070SQ/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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