Texas Instruments LMH0346MHX
- Part No.:
- LMH0346MHX
- Manufacturer:
- Texas Instruments
- Category:
- Video Processing
- Package:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LMH0346MHX.pdf
- Description:
- IC VIDEO RECLOCKER 20HTSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,009
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LMH0346MHX from Texas Instruments is a 3 Gbps HD/SD SDI reclocker IC that retimes serial digital video data conforming to SMPTE 424M (2.97 Gbps), SMPTE 292M (1.485 Gbps), and SMPTE 259M(C) (270 Mbps) standards, with dual differential outputs and automatic rate detection - deployed in broadcast-grade video routers, format converters, and DVB-ASI equipment.
For engineers reviewing the LMH0346MHX datasheet, LMH0346MHX pinout, LMH0346MHX application, or LMH0346MHX equivalent, key selection criteria include its 20-pin HTSSOP package, single 3.3V supply operation, 0.06–0.08 UIP-P output jitter at 3 Gbps, LVPECL-compatible I/O, and configurable second output as either reclocked data or low-jitter data-rate clock.
Technical Context
The LMH0346MHX implements a PLL-based reclocking architecture with two independent loop filters (LF1/LF2) and supports auto-detection across five discrete serial data rates: 270 Mbps, 1.483 Gbps, 1.485 Gbps, 2.967 Gbps, and 2.97 Gbps. It does not lock to harmonics (e.g., 143/177/360/540 Mbps) and enters bypass mode for unsupported rates.
Its dual differential outputs (SDO and SCO/SDO2) are CML-driven and LVPECL-compatible, delivering 750 mVP-P into 100 Ω differential loads; SCO/SDO2 is multiplexed via SCO_EN to output either retimed serial data or a phase-aligned serial clock (270 MHz / 1.485 GHz / 2.97 GHz) with ≤60% alignment tolerance relative to data interval center.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rates | 270 Mbps, 1.483/1.485 Gbps, 2.967/2.97 Gbps - fully compliant with SMPTE 424M, 292M, 259M(C), and DVB-ASI |
| Output Jitter (3 Gbps) | 0.06–0.08 UIP-P - suppresses accumulated cable-induced jitter for robust eye opening in 3G-SDI links |
| Supply Voltage | 3.3 V ±5% - single-rail operation simplifies power design vs. dual-supply alternatives |
| Power Consumption | 126 mA typical @ 2970 Mbps - ~370 mW total, enabling thermal management in dense video routing PCBs |
| Input Compatibility | Differential LVPECL/CML - accepts DC-coupled signals from equalizers like LMH0344 without level-shifting |
| Output Drive | 750 mVP-P into 100 Ω diff - meets SMPTE 424M amplitude requirements for driving LMH0302 cable drivers |
| Reference Clock | 27 MHz ±50 ppm crystal or LVCMOS input - enables stable PLL lock without external frequency synthesizers |
Pinout & Package
LMH0346MHX is packaged in a 20-pin HTSSOP (PWP) with exposed die attach pad (DAP) electrically connected to VEE (ground); DAP must be soldered to PCB ground plane for thermal integrity and signal reference stability.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 | LF1, LF2 | Loop filter terminals - require 56 nF capacitor between them; fixed value ensures stable PLL bandwidth per data rate |
| 3, 4 | RATE0, RATE1 | Manual rate select inputs - internal pulldowns default to Auto-Rate Detect (00); enable fixed-mode operation or test modes |
| 5, 6 | SDI, SDI | Differential serial data input - LVPECL-compatible, 200–1600 mVP-P, no internal termination; requires external 100 Ω differential termination |
| 7 | VCC | Core supply rail - 3.3 V input powering internal logic, PLL, and control circuitry |
| 8 | BYPASS/AUTO BYPASS | Reclocker enable/disable - internal pulldown enables Auto Bypass on unlock; high forces transparent pass-through |
| 9 | OUTPUT MUTE | Output disable control - internal pullup enables outputs by default; low mutes both SDO and SCO/SDO2 simultaneously |
| 10 | XTAL IN/EXT CLK | 27 MHz reference input - accepts parallel-resonant crystal or LVCMOS clock; defines PLL timing accuracy and jitter floor |
| 11 | XTAL OUT | Crystal oscillator output - drives external crystal in fundamental mode; not used with external clock input |
| 12 | LOCK DETECT | Active-high PLL lock indicator - asserts within 15 ms of valid input; used to gate OUTPUT MUTE or downstream sync logic |
| 13, 14 | SCO/SDO2, SCO/SDO2 | Multiplexed differential output - selected by SCO_EN as second data stream or data-rate clock (270 MHz / 1.485 GHz / 2.97 GHz) |
| 15, 16 | VCCO | Output driver supply - separate 3.3 V rail decoupling improves output signal integrity and reduces crosstalk |
| 17, 18 | SDO, SDO | Primary differential reclocked output - always active, 750 mVP-P, LVPECL-compatible, drives 100 Ω terminated loads |
| 19 | SD/HD | Data rate indicator - high = SD (270 Mbps), low = HD/3G (≥1.485 Gbps); registered output valid only when LOCK DETECT = high |
| 20 | SCO_EN | SCO/SDO2 function select - internal pulldown defaults to data output mode; high configures output as serial clock |
Key Features
| Feature | Design Value |
|---|---|
| Auto-Rate Detection | Identifies and locks to any supported SMPTE or DVB-ASI data rate without configuration - eliminates firmware dependency in field-upgradable gear |
| Dual Differential Outputs | One fixed SDO + one SCO/SDO2 configurable as data or clock - enables flexible fanout to multiple downstream devices (e.g., dual cable drivers or clock-synchronized processors) |
| Low-Jitter Serial Clock Output | 2.97 GHz clock with ≤3 psRMS jitter - provides clean timing reference for ADCs, FPGAs, or serializer/deserializer ICs in 3G-SDI systems |
| LVPECL-Compatible I/O | DC-coupled interface compatibility with TI's LMH0344 equalizer and LMH0302 driver - eliminates level shifters and reduces BOM count |
| Industrial Temperature Range | −40°C to +85°C operation - qualified for broadcast infrastructure deployed in uncontrolled rack environments |
Applications
| Broadcast Video Routers | Digital Video Format Converters |
|---|---|
|
Use Scenario: Re-timing SDI signals across multi-stage routing matrices with cascaded cable runs exceeding 100 m. IC Role / Device Role / Timing Role: Reclocker suppressing accumulated jitter from adaptive equalizers and long coaxial traces to maintain SMPTE-compliant eye diagrams. Use Value: Enables reliable 3G-SDI switching at full bandwidth without manual rate provisioning or firmware updates per source. |
Use Scenario: Converting between 1080i50, 1080p60, and UHD-SDI formats in real-time processing hardware. IC Role / Device Role / Timing Role: Jitter-cleaned data source for FPGA-based video scalers and color-space converters requiring stable bit-clock alignment. Use Value: Eliminates metastability in pixel-clock domain crossing by providing sub-0.1 UIP-P jitter at 2.97 Gbps. |
| DVB-ASI Equipment | Professional Camera Interface Modules |
|
Use Scenario: Retiming MPEG-2 transport streams over 75 Ω coax in satellite uplink encoders and modulators. IC Role / Device Role / Timing Role: SDI reclocker operating at 270 Mbps with DVB-ASI support - maintains 8B10B coding integrity and BER <10−12. Use Value: Prevents burst errors caused by intersymbol interference in long-haul ASI distribution networks. |
Use Scenario: Embedding timecode and ancillary data into camera output streams before transmission over fiber or IP. IC Role / Device Role / Timing Role: Reclocked SDI source feeding SMPTE 2022-6 compliant encoder ASICs requiring precise clock/data alignment. Use Value: Ensures <40% clock-to-data alignment margin for reliable parallel-to-serial conversion in camera head electronics. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SDI reclocking applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH0346SQ/NOPB | Same silicon, 24-pin WQFN package (5 mm × 4 mm) - smaller footprint but higher θJA (33.0°C/W vs. 26.6°C/W) | Preferred for space-constrained portable video encoders where thermal headroom allows | Select LMH0346SQ/NOPB when board area is critical and airflow supports WQFN thermal performance. |
| LMH0384SQ/NOPB | Pin-compatible upgrade with extended 12G-SDI support (11.88 Gbps), lower 0.03 UIP-P jitter, and integrated cable drive capability | Suitable for next-gen UHD/4K/8K infrastructure requiring backward compatibility with 3G-SDI | Choose LMH0384SQ/NOPB for future-proofing 12G-SDI designs while retaining LMH0346MHX layout compatibility. |
Compared with LMH0346SQ/NOPB, LMH0346MHX offers better thermal dissipation in HTSSOP packaging for sustained 3G-SDI operation; versus LMH0384SQ/NOPB, it lacks 12G-SDI capability but delivers identical 3G-SDI performance at lower cost and maturity for legacy broadcast deployments.
Availability
LMH0346MHX is available at Aetrix Electronics and suitable for broadcast video routers, digital video format converters, and DVB-ASI equipment requiring stable component supply across long production lifecycles and EOL-sensitive infrastructure programs.
Supply support for LMH0346MHX includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions for industrial, automotive, and communications markets.
The LMH0346MHX belongs to TI's high-speed serial interface product line, engineered specifically for SMPTE-compliant broadcast video infrastructure - emphasizing jitter suppression, multi-standard interoperability, and drop-in integration with TI's companion equalizers and drivers.
FAQ
What video standards does the LMH0346MHX support?
The LMH0346MHX supports SMPTE 424M (3G-SDI, 2.97 Gbps), SMPTE 292M (HD-SDI, 1.485 Gbps), SMPTE 259M(C) (SD-SDI, 270 Mbps), and DVB-ASI (270 Mbps). It automatically detects and locks to any of these rates without configuration. The LMH0346MHX does not support SMPTE 2081 (12G-SDI) or non-SMPTE protocols. Its compliance is verified per RP 184-1996 jitter tolerance testing.
How is the second output (SCO/SDO2) configured on the LMH0346MHX?
The SCO/SDO2 output on the LMH0346MHX is configured via the SCO_EN pin: when low (default, due to internal pulldown), it functions as a second reclocked serial data output; when high, it outputs a low-jitter, phase-aligned serial clock matching the detected data rate (270 MHz / 1.485 GHz / 2.97 GHz). The LMH0346MHX maintains ≤60% alignment tolerance between clock edge and data interval center.
Does the LMH0346MHX require external loop filter components?
Yes - the LMH0346MHX requires a 56 nF capacitor between pins LF1 and LF2 to set PLL loop bandwidth. This value is fixed and validated for all supported data rates (270 Mbps to 2.97 Gbps); deviation causes instability or failure to lock. No resistors or additional capacitors are needed. The LMH0346MHX datasheet explicitly states this is the only supported loop filter configuration.
What is the purpose of the SD/HD output pin on the LMH0346MHX?
The SD/HD pin on the LMH0346MHX is a registered status indicator: high indicates SD-SDI (270 Mbps) operation; low indicates HD-SDI or 3G-SDI (≥1.485 Gbps). It is only valid when LOCK DETECT is high; otherwise, it defaults to low (HD/3G). The LMH0346MHX uses this signal to configure downstream devices like the LMH0302 cable driver for correct edge-rate compliance per SMPTE standard.
Can the LMH0346MHX operate with an external 27 MHz clock instead of a crystal?
Yes - the LMH0346MHX accepts a 27 MHz LVCMOS-compatible clock signal applied to the XTAL IN/EXT CLK pin, eliminating the need for a crystal and associated load capacitors. When using external clock, the XTAL OUT pin is left unconnected. The LMH0346MHX specifies ±50 ppm frequency tolerance for stable PLL lock; clock duty cycle must be 45–55% and rise/fall times <1.5 ns.
LMH0346MHX Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-PowerTSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Reclocker
- Applications:
- Professional Video
- Standards:
- DVB-ASI, SMPTE
- Control Interface:
- Serial
- Voltage - Supply:
- 3.135V ~ 3.465V
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 20-HTSSOP
LMH0346MHX FAQ
1.How can I place an order for LMH0346MHX through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH0346MHX on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH0346MHX reliable?
The price and inventory of LMH0346MHX are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH0346MHX is usually 5 days.
3.What payment methods are accepted for LMH0346MHX?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMH0346MHX transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LMH0346MHX?
LMH0346MHX orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMH0346MHX order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH0346MHX?
For technical support, including LMH0346MHX datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH0346MHX requirements.
6.How does Aetrix verify that LMH0346MHX is sourced from the original manufacturer or authorized distributors?
All LMH0346MHX products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH0346MHX meets industry standards.
7.What is the process for return or replacement of LMH0346MHX?
All LMH0346MHX units undergo pre-shipment inspection (PSI). If there is an issue with LMH0346MHX, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH0346MHX part is unused and in its original packaging.
Return procedure for LMH0346MHX:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LMH0346MHX Tags

-
HDMI2C1-6C1
STMicroelectronics

-
ADA4430-1YKSZ-R7
Analog Devices Inc.

-
LM1881MX/NOPB
Texas Instruments

-
SN75DP130SSRGZR
Texas Instruments

-
EQCO30T5.2
Microchip Technology
-
LMH1980MM/NOPB
Texas Instruments

-
EQCO30R5.D
Microchip Technology

-
SII9022ACNU
Lattice Semiconductor Corporation

-
SN65DP159RGZR
Texas Instruments

-
SN65DP159RSBR
Texas Instruments

-
SN65DP141RLJR
Texas Instruments

-
LMH0303SQ/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

