Texas Instruments LMH0356SQX-40/NOPB
- Part No.:
- LMH0356SQX-40/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Video Processing
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
LMH0356SQX-40/NOPB.pdf
- Description:
- IC VIDEO RECLOCKER 40WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LMH0356SQX-40/NOPB from Texas Instruments is a 3-Gbps HD/SD SDI reclocker with integrated 4:1 input multiplexer, four FR4 equalizers (0–30 inch), dual differential LVPECL/CML outputs, and auto-rate detection for SMPTE ST-259/ST-292/ST-424 and DVB-ASI standards. It suppresses accumulated jitter in broadcast video routing and format conversion systems.
For engineers reviewing the LMH0356SQX-40/NOPB datasheet, LMH0356SQX-40/NOPB pinout, LMH0356SQX-40/NOPB application, or LMH0356SQX-40/NOPB equivalent, key selection factors include its 40-pin WQFN package, 270 Mbps to 2.97 Gbps data rate support, 0.08–0.09 UIP-P output jitter at 3 Gbps, 430-mW typical power, and LVCMOS control interface with lock detect and SD/HD rate indication.
Technical Context
The LMH0356SQX-40/NOPB implements a PLL-based retiming architecture with VCO and dual loop filters (LF1/LF2) for stable clock recovery across five discrete serial data rates. Its 4:1 mux selects one of four differential CML inputs (SDI0–SDI3), each with dedicated FR4 equalization capable of compensating up to 30 inches of lossy PCB trace.
It provides two differential outputs: SDO (primary retimed data) and SCO/SDO2 (configurable as second data or recovered clock), both LVPECL-compatible and 100-Ω differentially terminated. Control logic includes LVCMOS inputs (ENABLE, SEL0/SEL1, RATE0/RATE1, SCO_EN, BYPASS/AUTO BYPASS, OUTPUT MUTE) and indicator outputs (LOCK DETECT, SD/HD, RATE0/RATE1).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rates | 270 Mbps, 1.483/1.485 Gbps, 2.967/2.97 Gbps - supports SMPTE ST-259 (SD), ST-292 (HD), ST-424 (3G), and DVB-ASI |
| Output Jitter | 0.08–0.09 UIP-P at 2.97 Gbps - enables reliable signal integrity over long coaxial or backplane traces |
| Input Equalization | 0–30 inch FR4 per channel - compensates trace loss without external tuning or firmware |
| Power Supply | Single 3.3-V supply - simplifies board-level power design; 430-mW typical active, 10-mW in power-down mode |
| Package | 40-pin WQFN (5.0 mm × 5.0 mm) - space-efficient footprint compatible with high-density video interface layouts |
| Operating Temp | –40°C to +85°C - qualified for industrial and broadcast equipment environments |
| ESD Rating | ±8000 V HBM - robust handling in manufacturing and field service |
Pinout & Package
LMH0356SQX-40/NOPB uses a 40-pin WQFN package (5.0 mm × 5.0 mm) with exposed die attach pad connected to VEE (ground). Pin functions are validated per TI SNLS270L Rev L datasheet, Figure 6 (RSB Package, 40-Pin WQFN top view).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| SDI0 / SDI0 | Differential serial data input 0 | LVPECL/CML-compatible; internally 50-Ω terminated (100-Ω diff); accepts 270 Mbps–2.97 Gbps signals |
| SDI1 / SDI1, SDI2 / SDI2, SDI3 / SDI3 | Differential serial data inputs 1–3 | Each has independent FR4 equalizer; selected via SEL0/SEL1; same electrical interface as SDI0 |
| SDO / SDO | Primary differential retimed data output | LVPECL-compatible; 750 mVP-P into 100-Ω diff load; muted when OUTPUT MUTE = low |
| SCO/SDO2 / SCO/SDO2 | Configurable secondary output | Set by SCO_EN: data (low) or recovered clock (high); clock aligns within 10% of data bit center |
| LOCK DETECT | PLL lock status indicator | Active-high open-drain LVCMOS output; asserts only when locked to supported data rate |
| SD/HD | Data rate range indicator | LVCMOS output: high = 270 Mbps (SD), low = ≥1.483 Gbps (HD/3G); valid only when LOCK DETECT = high |
| ENABLE | Global device enable | LVCMOS input with internal pullup; disables core circuitry (430 mW → 10 mW) while preserving XTAL oscillator |
| XTAL IN/EXT CLK | 27-MHz reference clock input | Accepts parallel-resonant crystal or LVCMOS 27-MHz clock; ±50 ppm tolerance required |
| XTAL OUT | Crystal oscillator output | Drives external crystal; remains active even when ENABLE = low |
| BYPASS/AUTO BYPASS | Reclocking mode control | Internal pulldown; high = forced bypass (no retiming); low = auto-bypass on unlock or unsupported rate |
| OUTPUT MUTE | Output muting control | LVCMOS input with internal pullup; low = mutes both SDO and SCO/SDO2 regardless of bypass state |
| SEL0 / SEL1 | 4:1 input mux select | LVCMOS inputs with internal pulldowns; encode 00–11 to select SDI0–SDI3 per Table 2 |
| RATE0 / RATE1 | Manual data rate selection | LVCMOS inputs with internal pulldowns; set 00 = auto-detect, 01 = 270 Mbps, 10 = HD/3G rates |
| SCO_EN | SCO/SDO2 function select | LVCMOS input with internal pulldown; low = second data output, high = recovered clock output |
| VCC | Positive supply | 3.3-V ±5%; supplied to pins 3, 11, 13, 26, 29, 30 - decoupling required per layout guidelines |
| VEE | Negative supply / ground | Connected to exposed die attach pad and pins 12, 17, 18, 20, 33, 34 - primary return path for all signals |
| LF1 / LF2 | PLL loop filter connections | External RC networks set loop bandwidth: 275 kHz (270 Mbps), 1.5 MHz (1.485 Gbps), 2.75 MHz (2.97 Gbps) |
Key Features
| Feature | Design Value |
|---|---|
| 4-channel FR4 equalization | Each input independently equalizes 0–30 inches of FR4 trace - eliminates need for external equalizers or layout tuning |
| Auto-rate detection | Dynamically locks to 270/1483/1485/2967/2970 Mbps without manual configuration - reduces firmware overhead in multi-standard systems |
| Dual configurable outputs | SCO/SDO2 switches between second data stream or recovered clock - enables flexible clock distribution or dual-output fanout |
| Power-down mode | 10-mW standby current with ENABLE = low - preserves 27-MHz reference for cascaded reclockers while minimizing system power |
| LVCMOS control interface | All control/indicator pins use 3.3-V LVCMOS levels - direct interfacing with FPGAs, MCUs, and CPLDs without level shifters |
| Lock-synchronized indicators | SD/HD and LOCK DETECT outputs are registered and synchronized to PLL lock - prevents metastability in downstream logic |
Applications
| Broadcast Video Router | Digital Video Format Converter |
|---|---|
Use Scenario: High-density SDI routing matrix switching between 12G, 6G, 3G, HD, and SD sources in live production trucks. IC Role / Device Role / Timing Role: Reclocker and jitter cleaner on each input port; equalizes variable-length backplane traces before crosspoint switching. Use Value: Enables error-free switching across SMPTE standards by reducing input jitter below 0.09 UIP-P, preventing bit errors in downstream demultiplexers. | Use Scenario: Converting legacy SD-SDI feeds to modern 3G-SDI infrastructure in broadcast master control rooms. IC Role / Device Role / Timing Role: Input retimer with FR4 equalization on SDI0–SDI3; auto-detects 270 Mbps and retransmits at 2.97 Gbps with regenerated clock. Use Value: Eliminates need for separate SD-to-HD transcoders by providing clean, low-jitter 3G output directly from SD source with no frame buffer delay. |
| DVB-ASI Equipment | Video Processing Engine |
Use Scenario: MPEG-2 transport stream distribution in satellite uplink facilities using DVB-ASI over coaxial cable. IC Role / Device Role / Timing Role: Reclocker on ASI input line; equalizes cable-induced loss and suppresses jitter accumulated over 100+ meters of RG-6. Use Value: Maintains BER <1e−12 by meeting SMPTE RP 184-1996 jitter tolerance requirements at 270 Mbps, ensuring reliable TS packet delivery. | Use Scenario: Real-time video effects processing in FPGA-based hardware accelerators requiring precise timing alignment. IC Role / Device Role / Timing Role: Clock recovery and data retiming stage before pixel-domain processing; SCO/SDO2 configured as recovered clock for FPGA sampling. Use Value: Provides sub-100-ps RMS clock jitter (2–3 ps RMS) synchronized to data edges, enabling deterministic pixel sampling across multiple pipelines. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SDI reclocking applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH0356SQE-48/NOPB | 48-pin WQFN (7 mm × 7 mm); adds NC pins and extra VCC/VEE connections; identical electrical specs and pinout compatibility with LMH0056/LMH0036 | Used where board layout requires larger thermal pad or legacy footprint compatibility; not drop-in for 40-pin designs | Select LMH0356SQE-48/NOPB only if mechanical constraints require 48-pin package or co-design with LMH0056-based systems. |
| LMH0344RTWT | Adaptive cable equalizer (no reclocking); single-channel; supports up to 12G-SDI; no PLL, no outputs, no rate detection | Placed upstream of reclocker to extend cable reach; complements but does not replace LMH0356SQX-40/NOPB's retiming function | Use LMH0344RTWT in cascade with LMH0356SQX-40/NOPB for >100 m coax runs; never as standalone reclocker replacement. |
Compared with LMH0356SQE-48/NOPB and LMH0344RTWT, the LMH0356SQX-40/NOPB uniquely combines 4:1 muxing, per-channel FR4 equalization, auto-rate detection, and dual configurable outputs in a compact 5-mm WQFN - making it optimal for space-constrained, multi-standard SDI edge devices where full reclocking and jitter cleanup are mandatory.
Availability
LMH0356SQX-40/NOPB is available at Aetrix Electronics and suitable for broadcast video routers, digital video format converters, DVB-ASI equipment, and video processing engines requiring stable component supply and long-term lifecycle assurance.
Supply support for LMH0356SQX-40/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies for industrial, automotive, and communications markets.
The LMH0356 product line delivers high-speed serial digital video interface solutions - specifically engineered for SMPTE-compliant reclocking, equalization, and jitter attenuation in professional broadcast and production equipment.
FAQ
What video standards does the LMH0356SQX-40/NOPB support?
The LMH0356SQX-40/NOPB supports SMPTE ST-259 (270 Mbps SD-SDI), ST-292 (1.485 Gbps HD-SDI), ST-424 (2.97 Gbps 3G-SDI), and DVB-ASI (270 Mbps). It automatically detects and locks to these exact rates - 270, 1483, 1485, 2967, and 2970 Mbps - and does not lock to harmonics or unsupported rates like 360 or 540 Mbps.
How does the LMH0356SQX-40/NOPB handle input trace loss?
The LMH0356SQX-40/NOPB integrates four independent FR4 equalizers - one per SDI input (SDI0–SDI3) - each capable of compensating up to 30 inches of FR4 PCB trace loss. This equalization is automatic and requires no programming, calibration, or external components, making it ideal for variable-length interconnects in video switchers and routers.
Can the LMH0356SQX-40/NOPB generate a clean clock output?
Yes. When SCO_EN is high, the LMH0356SQX-40/NOPB configures SCO/SDO2 as a low-jitter recovered clock output aligned to the data bit interval within 10% of center. At 2.97 Gbps, clock jitter is specified at 2–3 psRMS, and output amplitude is 400–650 mVP-P into 100-Ω differential load.
What is the power consumption profile of the LMH0356SQX-40/NOPB?
The LMH0356SQX-40/NOPB consumes 430 mW typical during active operation at 2.97 Gbps. When ENABLE is driven low, it enters power-down mode drawing only 10 mW - while maintaining XTAL oscillator functionality to drive other devices. This dual-state power management supports energy-efficient broadcast equipment design.
Is the LMH0356SQX-40/NOPB pin-compatible with other TI SDI reclockers?
No. The LMH0356SQX-40/NOPB uses a unique 40-pin WQFN footprint. Its 48-pin variant (LMH0356SQE-48/NOPB) is footprint-compatible with LMH0056 and LMH0036, but the 40-pin version is not. Pin assignments, control logic, and functional blocks differ significantly across TI's LMH0xxx SDI portfolio - direct substitution requires schematic and layout revision.
LMH0356SQX-40/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Reclocker
- Applications:
- Professional Video
- Standards:
- DVB-ASI, SMPTE
- Control Interface:
- Serial
- Voltage - Supply:
- 3.135V ~ 3.465V
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 40-WQFN (5x5)
LMH0356SQX-40/NOPB FAQ
1.How can I place an order for LMH0356SQX-40/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH0356SQX-40/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH0356SQX-40/NOPB reliable?
The price and inventory of LMH0356SQX-40/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH0356SQX-40/NOPB is usually 5 days.
3.What payment methods are accepted for LMH0356SQX-40/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMH0356SQX-40/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LMH0356SQX-40/NOPB?
LMH0356SQX-40/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMH0356SQX-40/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH0356SQX-40/NOPB?
For technical support, including LMH0356SQX-40/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH0356SQX-40/NOPB requirements.
6.How does Aetrix verify that LMH0356SQX-40/NOPB is sourced from the original manufacturer or authorized distributors?
All LMH0356SQX-40/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH0356SQX-40/NOPB meets industry standards.
7.What is the process for return or replacement of LMH0356SQX-40/NOPB?
All LMH0356SQX-40/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMH0356SQX-40/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH0356SQX-40/NOPB part is unused and in its original packaging.
Return procedure for LMH0356SQX-40/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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