Texas Instruments LMH0384SQ/NOPB
- Part No.:
- LMH0384SQ/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 16-WQFN Exposed Pad
- Datasheet:
-
LMH0384SQ/NOPB.pdf
- Description:
- IC INTERFACE SPECIALIZED 16WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LMH0384SQ/NOPB from Texas Instruments is a 3-Gbps SDI adaptive cable equalizer designed for serial digital video signal recovery in broadcast and professional video systems. It equalizes signals over up to 140 m of Belden 1694A coax at 2.97 Gbps, supports SMPTE ST 424/292/344/259 standards, implements DC restoration for pathological data, and operates from a single 3.3-V supply in a 16-pin WQFN package.
For engineers reviewing the LMH0384SQ/NOPB datasheet, LMH0384SQ/NOPB pinout, LMH0384SQ/NOPB application, or LMH0384SQ/NOPB equivalent, key selection considerations include its dual-mode operation (pin-compatible with LMH0344 or SPI-programmable), auto-sleep power management (14 mA typical in power-save mode), configurable LVDS output swing (400–800 mVP-P), and carrier-detect–driven mute functionality for unattended signal integrity monitoring.
Technical Context
The LMH0384SQ/NOPB employs a multistage adaptive filter controlled by an external 1-µF AEC loop capacitor across AEC+ and AEC− pins, enabling real-time equalization adjustment based on input signal energy. Its DC restoration block fully restores baseline for SMPTE RP 178/RP 198-compliant pathological patterns without requiring external AC coupling.
In pin mode, it provides hardware-configurable functions via dedicated control pins (BYPASS, MUTE, AUTO SLEEP, CD); in SPI mode, it exposes register-level control of output common-mode voltage (1.05–1.85 V), differential swing, launch amplitude optimization, and cable-length indication-enabling fine-grained system tuning without layout changes.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate Range | 125 Mbps to 2.97 Gbps - covers SD, HD, and 3G-SDI standards including ST 259, ST 292, ST 344, and ST 424. |
| Cable Equalization | Up to 140 m Belden 1694A at 2.97 Gbps - enables long-haul routing in broadcast infrastructure without repeaters. |
| Supply Voltage | 3.135 V to 3.465 V - single 3.3-V rail operation simplifies power design and eliminates level-shifting requirements. |
| Output Type | Internally terminated 100-Ω LVDS - eliminates need for external termination resistors and reduces board space. |
| Power Consumption | 14 mA typical in power-save mode - reduces thermal load and extends uptime in fanless enclosures. |
| Jitter Performance | <0.35 UI at 2.97 Gbps over 140 m Belden 1694A - meets SMPTE RP 184/RP 192 jitter compliance for broadcast-grade video. |
| Operating Temperature | −40°C to +85°C - qualified for industrial and broadcast equipment deployed in uncontrolled environments. |
Pinout & Package
Package: 16-pin WQFN (RUM), 4.00 mm × 4.00 mm, exposed die attach pad (DAP) connected to VEE (ground).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 9, - (DAP) | Ground (VEE) | Primary ground reference and thermal path; DAP must be soldered to PCB ground plane for thermal and electrical integrity. |
| 2, 3 | Differential Input (SDI, SDI) | AC-coupled true/complement SDI inputs accepting 720–950 mVP-P swing; support single-ended or differential interface. |
| 4 | SPI Mode Select (SPI_EN) | LVCMOS input with internal pulldown; high = SPI register access, low = pin-mode compatibility with LMH0344. |
| 5, 6 | AEC Loop Filter (AEC+, AEC−) | Analog nodes for external 1-µF capacitor; sets adaptation bandwidth and stability of adaptive equalization loop. |
| 7 (Pin Mode) / 7 (SPI Mode) | BYPASS / CD | Pin Mode: bypasses equalization when high; SPI Mode: carrier detect output indicating valid input presence. |
| 8, 14 | MUTEREF / MUTE | MUTEREF sets CD threshold voltage (0.8–1.3 V range); MUTE forces LVDS outputs to logic zero when high. |
| 10, 11 | Differential Output (SDO, SDO) | Internally terminated 100-Ω LVDS outputs with programmable 400–800 mVP-P swing and 1.05–1.85 V common-mode voltage. |
| 12 | AUTO SLEEP | LVCMOS input with internal pullup; high enables automatic power-down within 200 µs when CD asserts (no signal detected). |
| 13, 16 | Power Supply (VCC) | +3.3 V supply pins; require local 0.1-µF ceramic decoupling per pin for stable high-speed operation. |
Key Features
| Feature | Design Value |
|---|---|
| Adaptive Equalization with DC Restoration | Self-biasing DC restoration handles SMPTE RP 178/RP 198 pathological sequences without baseline wander, eliminating need for external AC coupling capacitors. |
| Dual-Mode Operation | Pin-mode ensures drop-in replacement for LMH0344/LMH0044; SPI mode unlocks full configurability-including cable-length indicator and launch amplitude optimization-without changing PCB layout. |
| Programmable LVDS Outputs | Output swing (400–800 mVP-P) and common-mode voltage (1.05–1.85 V) adjustable via SPI to match diverse receiver input ranges, including 1.8-V crosspoint switches. |
| Auto Sleep with Fast Wake-up | Enters 14-mA power-save state within 200 µs of carrier loss and resumes full operation in <1 µs upon signal reacquisition-ideal for energy-sensitive broadcast transport links. |
| Carrier-Detect–Driven Muting | CD output and MUTEREF pin allow precise threshold-based muting of SDO/SDO when signal degrades beyond user-defined cable length or SNR margin. |
Applications
| Studio Camera Backhaul | Live Production Switcher Input |
|---|---|
Use Scenario: Transmitting uncompressed 1080p60 video from camera head to control room over 120 m of Belden 1694A coaxial cable. IC Role / Device Role / Timing Role: Adaptive equalizer restoring signal integrity at 2.97 Gbps while maintaining SMPTE ST 424 jitter compliance. Use Value: Eliminates need for active repeaters or fiber conversion, reducing latency and system cost while preserving broadcast-grade timing accuracy. | Use Scenario: Feeding multiple SDI sources into a 32×32 video matrix switcher with variable cable lengths (20–80 m). IC Role / Device Role / Timing Role: Input-stage equalizer normalizing signal amplitude and jitter across heterogeneous source cables before reclocking. Use Value: Ensures consistent eye opening and BER performance at switcher inputs, preventing frame drops during source switching. |
| Remote Broadcast Truck Interface | OB Van Signal Distribution |
Use Scenario: Receiving contribution feeds from remote venues via rented coax infrastructure with unknown aging and impedance variation. IC Role / Device Role / Timing Role: Robust cable equalizer with auto-sleep and carrier detect, adapting to marginal signal conditions without manual intervention. Use Value: Maintains lock on degraded signals down to 125 Mbps (SD-SDI), enabling fallback operation during transmission impairments. | Use Scenario: Distributing a master 3G-SDI reference clock and program feed to on-board monitors, recorders, and graphics engines. IC Role / Device Role / Timing Role: Signal conditioner providing jitter-cleaned, amplitude-stabilized outputs with programmable swing to match varied receiver thresholds. Use Value: Prevents timing skew and metastability in downstream devices by delivering consistent LVDS drive levels across all distribution paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar SDI equalizer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH0344SQ/NOPB | Fixed equalization profile; no SPI interface; no auto sleep; lower max data rate (1.5 Gbps). | Limited to HD-SDI (1.485 Gbps) and below; no cable-length adaptation or power management. | Select when footprint compatibility is required and 3G-SDI support or programmability is unnecessary. |
| GS2971-IBE3 | Supports 3G/HD/SD-SDI with integrated reclocking; requires external clock; higher power (125 mA typical). | Provides jitter cleaning + equalization; suited for retiming-critical paths where equalization alone is insufficient. | Select when system requires deterministic jitter reduction and clock regeneration-not just cable loss compensation. |
Compared with LMH0344SQ/NOPB, the LMH0384SQ/NOPB adds 3G-SDI support, adaptive response, and power-save capability; compared with GS2971-IBE3, it offers lower power, simpler biasing, and no external clock dependency-making it optimal for pure equalization tasks in space- and thermal-constrained enclosures.
Availability
LMH0384SQ/NOPB is available at Aetrix Electronics and suitable for broadcast infrastructure, live production switchers, and remote OB van signal conditioning requiring stable component supply, long-lifecycle assurance, and SMPTE-compliant signal integrity.
Supply support for LMH0384SQ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions for industrial, automotive, and communications markets.
The LMH0384SQ/NOPB belongs to TI's high-speed interface product line, engineered specifically for SMPTE-compliant serial digital video transport-balancing adaptive signal recovery, low-power operation, and seamless integration into broadcast-grade hardware.
FAQ
What is the maximum cable length the LMH0384SQ/NOPB can equalize at 2.97 Gbps?
The LMH0384SQ/NOPB equalizes up to 140 meters of Belden 1694A coaxial cable at 2.97 Gbps while maintaining SMPTE RP 184-compliant jitter performance. This capability is verified per characterization data in the official datasheet (SNLS308G, Section 6.6), and assumes standard 75-Ω impedance and proper AC-coupled input interface. Longer reach requires lower data rates or alternate cable types.
Does the LMH0384SQ/NOPB support both pin-mode and SPI-mode configuration?
Yes, the LMH0384SQ/NOPB supports two distinct operational modes. When SPI_EN is driven low, it operates in pin mode-footprint compatible with LMH0344SQ/NOPB and enabling hardware-only control via BYPASS, MUTE, and AUTO SLEEP pins. When SPI_EN is driven high, it enters SPI mode, exposing full register-level control of output swing, common-mode voltage, cable-length indication, and launch amplitude optimization.
How does the auto sleep function work in the LMH0384SQ/NOPB?
The LMH0384SQ/NOPB auto sleep function powers down the equalizer core within 200 µs when no valid input signal is detected (as indicated by the CD pin going high). It wakes automatically in under 1 µs upon signal reacquisition. This behavior is enabled by driving the AUTO SLEEP pin high; when low, auto sleep is disabled. In SPI mode, an additional register-controlled deep-sleep option allows forced power-down regardless of signal presence.
Can the LMH0384SQ/NOPB outputs interface directly with 1.8-V receivers?
Yes, the LMH0384SQ/NOPB outputs can interface directly with 1.8-V receivers. Its LVDS outputs feature programmable common-mode voltage (1.05–1.85 V) and differential swing (400–800 mVP-P) via SPI registers-allowing precise matching to low-voltage crosspoint switches and FPGAs. No level-shifting circuitry is needed when configured appropriately, reducing component count and signal path complexity.
What external components are required for basic LMH0384SQ/NOPB operation?
For basic pin-mode operation, the LMH0384SQ/NOPB requires only three external components: a 1-µF capacitor between AEC+ and AEC− pins for loop filter stability, and two 0.1-µF ceramic decoupling capacitors-one each on VCC pins 13 and 16. All other functions (DC restoration, termination, mute control) are fully integrated; no external resistors or AC-coupling capacitors are needed for standard SDI interface compliance.
LMH0384SQ/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 16-WQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Digital Interface
- Interface:
- SPI Serial
- Voltage - Supply:
- 3.135V ~ 3.465V
- Supplier Device Package:
- 16-WQFN (4x4)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
LMH0384SQ/NOPB FAQ
1.How can I place an order for LMH0384SQ/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH0384SQ/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH0384SQ/NOPB reliable?
The price and inventory of LMH0384SQ/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH0384SQ/NOPB is usually 5 days.
3.What payment methods are accepted for LMH0384SQ/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMH0384SQ/NOPB transactions.
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4.How is shipping managed for LMH0384SQ/NOPB?
LMH0384SQ/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMH0384SQ/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH0384SQ/NOPB?
For technical support, including LMH0384SQ/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH0384SQ/NOPB requirements.
6.How does Aetrix verify that LMH0384SQ/NOPB is sourced from the original manufacturer or authorized distributors?
All LMH0384SQ/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH0384SQ/NOPB meets industry standards.
7.What is the process for return or replacement of LMH0384SQ/NOPB?
All LMH0384SQ/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMH0384SQ/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH0384SQ/NOPB part is unused and in its original packaging.
Return procedure for LMH0384SQ/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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