My Inquiry
My Account
Texas Instruments LMH1982SQX/NOPB
- Part No.:
- LMH1982SQX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Video Processing
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
LMH1982SQX/NOPB.pdf
- Description:
- IC VIDEO CLOCK GENERATOR 32WQFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,945
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LMH1982SQX/NOPB from Texas Instruments is a multi-rate video clock generator IC designed for genlock synchronization in 3G/HD/SD-SDI systems. It delivers two simultaneous LVDS output clocks (SD_CLK at 27/67.5 MHz and HD_CLK at 74.25/74.176/148.5/148.35 MHz), a programmable Top of Frame (TOF) pulse, and supports dual reference inputs (REF_A/REF_B) with H/V sync detection. It is used in FPGA-based SDI SerDes clock recovery and broadcast video timing systems.
For engineers reviewing the LMH1982SQX/NOPB datasheet, LMH1982SQX/NOPB pinout, LMH1982SQX/NOPB application, or LMH1982SQX/NOPB equivalent, key selection criteria include genlock jitter performance (as low as 40 ps peak-to-peak TIE), dual-reference cross-locking capability, VCXO-based PLL architecture with external loop filter control, and I²C programmability for format-specific TOF timing alignment across NTSC, PAL, 720p, and 1080p standards.
Technical Context
The LMH1982SQX/NOPB implements a two-stage analog PLL architecture: PLL 1 uses an external 27 MHz VCXO and user-configurable loop filter to achieve low-jitter genlock to H/V sync references; PLLs 2–4 use integrated VCOs to generate SD and HD clocks with fixed multiplication ratios (e.g., ×2.5 for 67.5 MHz, ×2.75/×5.5 for 74.25/148.5 MHz). The device supports both free-run and holdover operation on reference loss, with VC_FREERUN bias voltage determining output accuracy during free-run mode.
It features dual LVDS clock outputs (SD_CLK and HD_CLK) with Hi-Z disable, a programmable LVCMOS TOF pulse synchronized to frame boundaries, and real-time status flags (NO_REF, NO_LOCK). Reference selection between REF_A and REF_B is configurable via I²C or hardware pin (REF_SEL), and genlock mode is controlled by GENLOCK pin or register bit GNLK.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Clocks | Two independent LVDS outputs: SD_CLK (27 MHz or 67.5 MHz) and HD_CLK (74.25, 74.176, 148.5, or 148.35 MHz) |
| TIE Jitter (Typ.) | 40 ps peak-to-peak for 74.25 MHz HD_CLK output - meets SMPTE SDI transmitter jitter specs when driving FPGA SerDes |
| TOF Pulse | Programmable LVCMOS Top of Frame signal with format-specific timing offset (e.g., TOF_OFFSET = 262 for NTSC, 312 for PAL) |
| Reference Inputs | Dual LVCMOS H/V sync ports (REF_A and REF_B); supports analog sync separators (e.g., LMH1981) or digital SDI deserializer timing |
| Supply Voltages | 3.3 V (VDD) and 2.5 V (DVDD); total typical power consumption ≈ 250 mW at genlock operation |
| Package | 32-pin WQFN (5.0 mm × 5.0 mm); thermal resistance RθJA = 33 °C/W |
| Control Interface | I²C-compatible (SDA/SCL pins with 4.7 kΩ pull-ups); register-mapped configuration for PLL dividers, TOF timing, and lock thresholds |
Pinout & Package
LMH1982SQX/NOPB is housed in a 32-pin WQFN package (5.0 mm × 5.0 mm) with exposed die attach pad (DAP) connected to GND. Pin functions are fully defined per TI SNLS289D Rev. D datasheet.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VC_FREERUN (1) | Analog input | Bias voltage setting for free-run frequency accuracy; must match external VCXO control range and be noise-filtered |
| HREF_A / VREF_A (4,5) | Digital input | H and V sync timing inputs for primary reference; compatible with LVCMOS levels (0.3VDD/0.7VDD thresholds) |
| REF_SEL (6) | Digital input | Selects REF_A or REF_B as active reference source; overrideable via I²C register PIN6_OVRD |
| GENLOCK (14) | Digital input | Hardware mode select for genlock vs. free-run; default-controlled by I²C register I2C_GNLK |
| SDA / SCL (11,12) | I²C bidirectional | Configures PLL dividers, TOF timing registers, lock thresholds, and output initialization sequence |
| SD_CLK / HD_CLK (23–24, 19–20) | LVDS output | Differential clock outputs with 100 Ω termination; each pair supports Hi-Z disable to reduce crosstalk and power |
| TOF (25) | LVCMOS output | Frame-aligned pulse with programmable delay (tD_TOF = 2 ns typical); used for frame buffer write/read synchronization |
| LPF (31) | Analog output | VCXO PLL loop filter node; external RC network sets loop bandwidth, jitter transfer, and lock time |
| VCXO (29) | LVCMOS input | 27 MHz VCXO clock input; drives all internal PLLs; jitter performance directly impacts output clock purity |
| NO_REF / NO_LOCK (16,17) | LVCMOS output | Status flags indicating reference presence and PLL lock; enable system-level fault detection and failover logic |
Key Features
| Feature | Design Value |
|---|---|
| Multi-standard genlock support | Configurable for NTSC, PAL, 720p, 1080i/p, and AES-47 48 kHz sample clock via register-programmed PLL dividers and TOF counters |
| Low-jitter clock synthesis | 40 ps peak-to-peak TIE jitter on 74.25 MHz HD_CLK enables direct connection to FPGA SerDes without additional jitter cleaning |
| Flexible reference handling | Dual reference ports with cross-locking allow seamless switchover between primary and backup sync sources during loss-of-reference events |
| Programmable TOF timing | TOF_OFFSET register (e.g., 262 for NTSC, 1124 for 1080p/24) aligns pulse to exact frame boundary, critical for video capture and frame buffer management |
| External loop filter control | LPF pin provides full analog control over PLL 1 bandwidth (typically <100 Hz), minimizing jitter transfer from noisy sync references |
Applications
| Video Genlock System | FPGA SDI SerDes Timing |
|---|---|
|
Use Scenario: Broadcast camera chain requiring precise frame-synchronous switching between multiple video sources. IC Role / Device Role / Timing Role: LMH1982SQX/NOPB generates genlocked SD and HD clocks plus TOF pulse aligned to incoming H/V sync, enabling zero-frame-delay switching. Use Value: Eliminates frame tearing and audio-video misalignment by maintaining sub-microsecond phase coherence across all sources. |
Use Scenario: High-speed video processing board using Xilinx or Intel FPGA with integrated SDI SerDes IP. IC Role / Device Role / Timing Role: LMH1982SQX/NOPB supplies low-jitter recovered clock (74.25/148.5 MHz) and TOF signal to FPGA's SerDes and frame buffer controller. Use Value: Meets SMPTE ST 425-1 jitter compliance without external jitter cleaners, reducing BOM count and PCB area. |
| Triple-Rate SDI Transmitter | Professional Video Converter |
|
Use Scenario: 3G-SDI transmitter module supporting SD, HD, and 3G rates in a single hardware design. IC Role / Device Role / Timing Role: LMH1982SQX/NOPB dynamically selects output frequencies (27/67.5/74.25/148.5 MHz) and TOF format based on detected input standard. Use Value: Enables software-defined rate switching without hardware changes or clock tree redesign. |
Use Scenario: HDMI-to-SDI converter requiring accurate frame timing translation between consumer and broadcast domains. IC Role / Device Role / Timing Role: LMH1982SQX/NOPB accepts HDMI-derived sync (via LMH1981) and generates SMPTE-compliant SDI clocks and TOF for encoder timing. Use Value: Maintains lip-sync integrity and prevents frame drops during format conversion by preserving original frame structure. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rate video clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMH1981 | Video sync separator (not clock generator); outputs H/V sync only - requires external PLL or clock chip for clock generation | Used upstream to extract timing from analog video; cannot replace LMH1982SQX/NOPB's clock synthesis or TOF generation | Select LMH1981 only when needing analog sync extraction prior to LMH1982SQX/NOPB; not a functional substitute |
| Si5338A-D-GM | Programmable clock generator with integrated crystal; supports wider frequency range but lacks native H/V sync input and TOF generation | Suitable for general-purpose timing; requires FPGA or MCU to implement frame-aligned TOF logic and sync detection | Choose Si5338A-D-GM for non-genlock applications or where H/V sync inputs are unavailable; adds firmware complexity for video timing |
Compared with LMH1982SQX/NOPB, LMH1981 serves only as a sync source and cannot generate clocks, while Si5338A-D-GM offers broader frequency flexibility but lacks dedicated video timing features like H/V sync decoding and programmable TOF - making LMH1982SQX/NOPB uniquely suited for SMPTE-compliant genlock systems.
Availability
LMH1982SQX/NOPB is available at Aetrix Electronics and suitable for broadcast equipment, FPGA-based SDI transceivers, and professional video converters requiring stable component supply, long-term lifecycle support, and traceable sourcing.
Supply support for LMH1982SQX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-reliability silicon for industrial, automotive, and communications markets.
The LMH1982SQX/NOPB belongs to TI's broadcast video timing product line, engineered specifically for SMPTE-compliant genlock, multi-format SDI clock generation, and frame-accurate synchronization in professional video infrastructure.
FAQ
What video standards does the LMH1982SQX/NOPB support?
The LMH1982SQX/NOPB supports NTSC (525i), PAL (625i), 720p (24–60 fps), 1080i/p (23.98–60 fps), and AES-47 48 kHz sample clock standards. Configuration is achieved via I²C registers that set PLL feedback dividers (e.g., FB_DIV = 1716 for NTSC), TOF_LPFM counters, and TOF_OFFSET values (e.g., 262 for NTSC). All timing parameters are validated per SMPTE RP 188 and ITU-R BT.601/656.
How does the LMH1982SQX/NOPB achieve low output jitter?
The LMH1982SQX/NOPB achieves low jitter through its two-stage PLL architecture: PLL 1 locks an external 27 MHz VCXO to H/V sync using a user-tuned analog loop filter (LPF pin), providing a clean, low-phase-noise reference; PLLs 2–4 then multiply this stable VCXO clock with high-bandwidth integrated VCOs. This separation ensures jitter transfer from the sync reference is attenuated, yielding as low as 40 ps peak-to-peak TIE on 74.25 MHz HD_CLK output.
Can the LMH1982SQX/NOPB operate without an external VCXO?
No - the LMH1982SQX/NOPB requires an external 27.0000 MHz VCXO connected to the VCXO pin (29). The device has no internal oscillator; PLL 1 relies entirely on this externally biased crystal for frequency stability and low phase noise. Omitting the VCXO prevents genlock operation and disables all clock outputs. The VC_FREERUN pin (1) only sets free-run frequency accuracy - it does not replace the VCXO.
What is the function of the LPF pin on the LMH1982SQX/NOPB?
The LPF pin (31) is the output node of PLL 1's charge pump, connecting to an external passive loop filter (typically RC network). This filter determines PLL 1's loop bandwidth, jitter transfer function, and lock acquisition time. A narrow bandwidth (<100 Hz) minimizes jitter transfer from noisy sync references, while wider bandwidth improves lock speed. TI provides recommended component values in SNLS289D Figure 11 for NTSC/PAL and HD formats.
Does the LMH1982SQX/NOPB support automatic reference switchover?
Yes - the LMH1982SQX/NOPB supports automatic reference switchover between REF_A and REF_B using the NO_REF status flag and I²C-controlled REF_SEL register. When NO_REF asserts (indicating loss of primary reference), firmware can reconfigure REF_SEL to select the secondary port. Cross-locking capability allows the device to maintain phase continuity during switchover, avoiding frame glitches in broadcast switchers and routers.
LMH1982SQX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Function:
- Generator
- Applications:
- Professional Video
- Standards:
- NTSC, PAL, SMPTE
- Control Interface:
- I2C
- Voltage - Supply:
- 3.135V ~ 3.465V
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 32-WQFN (5x5)
LMH1982SQX/NOPB FAQ
1.How can I place an order for LMH1982SQX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH1982SQX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH1982SQX/NOPB reliable?
The price and inventory of LMH1982SQX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH1982SQX/NOPB is usually 5 days.
3.What payment methods are accepted for LMH1982SQX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMH1982SQX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LMH1982SQX/NOPB?
LMH1982SQX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMH1982SQX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH1982SQX/NOPB?
For technical support, including LMH1982SQX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH1982SQX/NOPB requirements.
6.How does Aetrix verify that LMH1982SQX/NOPB is sourced from the original manufacturer or authorized distributors?
All LMH1982SQX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH1982SQX/NOPB meets industry standards.
7.What is the process for return or replacement of LMH1982SQX/NOPB?
All LMH1982SQX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMH1982SQX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH1982SQX/NOPB part is unused and in its original packaging.
Return procedure for LMH1982SQX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LMH1982SQX/NOPB Tags
-
HDMI2C1-6C1
STMicroelectronics
-
ADA4430-1YKSZ-R7
Analog Devices Inc.
-
LM1881MX/NOPB
Texas Instruments
-
SN75DP130SSRGZR
Texas Instruments
-
EQCO30T5.2
Microchip Technology
-
LMH1980MM/NOPB
Texas Instruments
-
EQCO30R5.D
Microchip Technology
-
SII9022ACNU
Lattice Semiconductor Corporation
-
SN65DP159RGZR
Texas Instruments
-
SN65DP159RSBR
Texas Instruments
-
SN65DP141RLJR
Texas Instruments
-
LMH0303SQ/NOPB
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
