Texas Instruments LMH6517SQX/NOPB
- Part No.:
- LMH6517SQX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Special Purpose Amplifiers
- Package:
- 32-WFQFN Exposed Pad
- Datasheet:
-
LMH6517SQX/NOPB.pdf
- Description:
- IC OPAMP VGA 2 CIRCUIT 32WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,361
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LMH6517SQX/NOPB from Texas Instruments is a dual-channel, digitally controlled variable-gain amplifier (DVGA) optimized for IF and baseband signal conditioning in high-performance ADC driver applications. It delivers 0.5 dB gain steps across a 31.5 dB range (−9.5 dB to +22 dB), features 200 Ω differential input impedance, 43 dBm OIP3 at 200 MHz, and operates on a single 5 V supply with 80 mA per channel supply current.
For engineers reviewing the LMH6517SQX/NOPB datasheet, LMH6517SQX/NOPB pinout, LMH6517SQX/NOPB application, or LMH6517SQX/NOPB equivalent, key selection criteria include gain step accuracy (±0.05 dB), channel-to-channel crosstalk (−85 dBc at 100 MHz), differential output swing (5.9 VPP), and support for parallel, SPI-compatible serial, and pulse-mode digital control - all critical for AGC loops in wide-dynamic-range receivers.
Technical Context
The LMH6517SQX/NOPB integrates two independent digitally controlled attenuators followed by high-linearity differential output amplifiers. Each channel uses a resistor-ladder-based attenuator with on-chip latches for gain state retention, enabling stable operation without continuous bus activity.
Its architecture supports three mutually exclusive digital interfaces: parallel 6-bit gain control (A0–A5/B0–B5), SPI-compatible serial mode (SDI/SDO/CS/CLK), and pulse-mode up/down control (UPA/UPB/DNA/DNB). Gain switching time is 15 ns, and phase shift variation across gain steps is ≤0.5°, preserving signal integrity in I/Q and phased-array systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| OIP3 | 43 dBm at 200 MHz - enables high SFDR in wideband IF sampling receivers before ADC saturation |
| Noise Figure | 5.5 dB at maximum gain - sets system noise floor when driving high-resolution ADCs like ADC16DV160 |
| Gain Range | −9.5 dB to +22 dB (31.5 dB total) - supports automatic gain control over >100 dB dynamic range in cellular base stations |
| Gain Step Accuracy | ±0.05 dB - ensures precise amplitude matching between I/Q channels in coherent receiver architectures |
| Supply Current | 80 mA per channel at 5 V - enables low-power operation while maintaining RF linearity up to 400 MHz |
| Input Impedance | 200 Ω differential - simplifies interface to 100 Ω or 50 Ω sources via LC matching networks or baluns |
| Output Swing | 5.9 VPP differential - delivers full-scale drive to 16-bit ADCs (e.g., ADC16DV160) with headroom on 5 V supply |
Pinout & Package
LMH6517SQX/NOPB is housed in a thermally enhanced 32-pin WQFN package (RTV0032A) with exposed thermal pad bonded to GND. Pin count and layout match TI's SP16160CH1RB reference design board.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IPA+, IPA− / IPB+, IPB− | Differential analog inputs (Ch A / Ch B) | 200 Ω self-biased inputs; require AC coupling or external CM biasing to avoid clipping beyond 0–5 V rail |
| OPA+, OPA− / OPB+, OPB− | Differential analog outputs (Ch A / Ch B) | Low-impedance outputs; support >5 VPP swing with 2.5 V common-mode; drive filters or ADCs directly |
| ENA, ENB | Channel enable (active-high) | Disables respective channel to 7.5 mA quiescent current; enables power gating in multi-channel AGC systems |
| A0–A5, B0–B5 | Parallel gain control bits (Ch A / Ch B) | 6-bit word sets gain in 0.5 dB steps; LSB = A0/B0 (0.5 dB), MSB = A5/B5 (16 dB) |
| LATA, LATB | Gain latch enable (active-low) | Freezes gain setting; prevents glitches during digital bus transitions - essential for stable AGC hold |
| MOD0, MOD1 | Mode selection (serial/parallel/pulse) | MOD1=1, MOD0=1 → parallel; MOD1=1, MOD0=0 → SPI serial; MOD1=0, MOD0=1 → pulse mode |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent DVGA channels | Enables simultaneous I/Q path gain control without inter-channel crosstalk (−85 dBc @ 100 MHz) |
| 0.5 dB gain resolution with ±0.05 dB accuracy | Supports fine-grained AGC in narrowband receivers where 1 dB steps cause SNR degradation |
| Three digital interface modes | Parallel (fastest), SPI serial (bus-efficient), or pulse (minimal GPIO); eliminates need for external logic |
| On-chip gain latches | Retains gain setting during microcontroller sleep or bus contention - critical for low-latency AGC hold |
| Single 5 V supply operation | Eliminates dual-rail supplies in space-constrained IF boards; compatible with standard LDOs and PMICs |
| Thermally enhanced WQFN package | θJA = 42°C/W enables sustained 160 mA total supply current without derating in compact layouts |
Applications
| Cellular Base Station Receiver | IF Sampling Receiver |
|---|---|
|
Use Scenario: Wide-dynamic-range downconversion of LTE/5G signals in macrocell BTS with strong adjacent-channel interferers. IC Role / Device Role / Timing Role: Dual-channel DVGA provides real-time AGC before 16-bit dual-channel ADC (e.g., ADC16DV160), maintaining SNR across >100 dB input power range. Use Value: 43 dBm OIP3 and −78 dBc IMD3 at 200 MHz prevent distortion-induced desensitization under blocker conditions. |
Use Scenario: High-fidelity digitization of 192 MHz IF signals in software-defined radio front ends. IC Role / Device Role / Timing Role: Differential driver conditions signal for ADC sampling; gain steps adjust to maintain optimal ADC input level despite varying RF path loss. Use Value: 0.5 dB gain resolution and <0.5° phase shift variation preserve I/Q balance and EVM in QAM-256 systems. |
| Instrumentation Signal Chain | Communications Modem Front End |
|
Use Scenario: Precision wideband signal generation and analysis in automated test equipment requiring calibrated amplitude control. IC Role / Device Role / Timing Role: Dual-path DVGA serves as programmable gain stage in calibration loop, with channel matching (±0.05 dB gain, ±0.1° phase) ensuring traceability. Use Value: On-chip gain latches eliminate bus timing constraints during measurement cycles, improving repeatability. |
Use Scenario: Adaptive gain control in cable modem upstream receivers handling DOCSIS 4.0 burst-mode signals with rapid power fluctuations. IC Role / Device Role / Timing Role: Pulse-mode control (UPA/UPB/DNA/DNB) enables sub-20 ns gain updates synchronized to burst preamble detection. Use Value: 15 ns gain switching time allows AGC convergence within first symbol period, minimizing packet loss. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-channel digitally controlled amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| ADL5330ACPZ-R7 | Single-channel, 0.5 dB steps, 30 dB range, 5.5 GHz bandwidth, requires dual 5 V/−5 V supplies | Higher frequency coverage but lacks dual-channel integration and latch functionality | Select when >1 GHz IF bandwidth is required and board space permits discrete channel duplication |
| LMH6518SQX/NOPB | Same pinout and feature set, but includes integrated 2:1 multiplexer per channel and higher 50 dB gain range | Supports TDD/FDD switchable paths; adds 2.5 mA/channel quiescent overhead | Select when signal routing flexibility (e.g., antenna diversity switching) is needed alongside DVGA function |
Compared with ADL5330ACPZ-R7 and LMH6518SQX/NOPB, LMH6517SQX/NOPB offers optimal trade-off of dual-channel integration, latch-based gain stability, and 5 V single-supply operation - making it preferred for space-constrained, low-power IF sampling systems where channel correlation and deterministic timing are critical.
Availability
LMH6517SQX/NOPB is available at Aetrix Electronics and suitable for cellular base station receivers, IF sampling receivers, instrumentation signal chains, and communications modem front ends requiring stable component supply and long-term production continuity.
Supply support for LMH6517SQX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in high-speed data converters and precision amplifiers.
The LMH6517SQX/NOPB belongs to TI's high-performance RF amplifier product line, designed specifically for digitally controlled gain applications in wireless infrastructure, test equipment, and broadband communications where linearity, gain accuracy, and thermal efficiency are paramount.
FAQ
What is the maximum operating frequency range of the LMH6517SQX/NOPB?
The LMH6517SQX/NOPB is characterized for operation up to 400 MHz, with specified performance including OIP3 (43 dBm), IMD3 (−78 dBc), and group delay flatness validated to 300 MHz. Its usable small-signal bandwidth exceeds 1.2 GHz, but linear performance degrades above 400 MHz - making it ideal for IF sampling up to 300 MHz rather than direct RF amplification.
Does the LMH6517SQX/NOPB support single-ended input configurations?
No - the LMH6517SQX/NOPB is designed exclusively for differential input operation. Its internal input stage is self-biased for 200 Ω differential impedance. Single-ended sources must be converted using an external balun or transformer, as demonstrated on TI's SP16160CH1RB reference board. Attempting single-ended drive risks common-mode imbalance and degraded distortion performance.
How does the LMH6517SQX/NOPB handle gain state retention during power cycling?
The LMH6517SQX/NOPB does not retain gain settings across power cycles - its on-chip registers reset to default (maximum gain) upon power-up. However, the parallel-mode latches (LATA/LATB) hold gain states indefinitely while powered, eliminating need for continuous bus refresh. For persistent storage, external non-volatile memory or microcontroller initialization code must reload the desired gain code after startup.
What is the thermal pad connection requirement for the LMH6517SQX/NOPB WQFN package?
The exposed thermal pad of the LMH6517SQX/NOPB (pin center pad) must be soldered to a solid GND plane using ≥4 thermal vias (0.3 mm diameter) spaced evenly beneath the pad. TI specifies θJA = 42°C/W only when the pad is properly connected; omitting this reduces thermal performance by >30%, risking junction temperature exceedance above 85°C ambient at full load.
Can the LMH6517SQX/NOPB drive a 100 Ω differential ADC input directly?
Yes - the LMH6517SQX/NOPB's low-impedance differential outputs can drive 100 Ω loads directly, delivering up to 5.9 VPP swing. However, for optimal harmonic distortion (e.g., −78 dBc IMD3), TI recommends back-terminating with 100 Ω at the ADC input and using short, controlled-impedance traces. The device's output impedance remains near 0 Ω, so no series matching is required.
LMH6517SQX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 32-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Type:
- ADC Driver
- Applications:
- Mobile Communications
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 32-WQFN (5x5)
LMH6517SQX/NOPB FAQ
1.How can I place an order for LMH6517SQX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMH6517SQX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMH6517SQX/NOPB reliable?
The price and inventory of LMH6517SQX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMH6517SQX/NOPB is usually 5 days.
3.What payment methods are accepted for LMH6517SQX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMH6517SQX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LMH6517SQX/NOPB?
LMH6517SQX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMH6517SQX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMH6517SQX/NOPB?
For technical support, including LMH6517SQX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMH6517SQX/NOPB requirements.
6.How does Aetrix verify that LMH6517SQX/NOPB is sourced from the original manufacturer or authorized distributors?
All LMH6517SQX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMH6517SQX/NOPB meets industry standards.
7.What is the process for return or replacement of LMH6517SQX/NOPB?
All LMH6517SQX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMH6517SQX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMH6517SQX/NOPB part is unused and in its original packaging.
Return procedure for LMH6517SQX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LMH6517SQX/NOPB Tags

-
TSM103WIDT
STMicroelectronics

-
LM392M/NOPB
Texas Instruments

-
MCP6S93T-E/UN
Microchip Technology

-
INA137UA/2K5
Texas Instruments

-
INA134UA/2K5
Texas Instruments

-
TS34118CS28 RDG
Taiwan Semiconductor Corporation

-
SI8920BC-IPR
Skyworks Solutions Inc.

-
ADUM3190ARQZ-RL7
Analog Devices Inc.

-
ADUM3190ARQZ
Analog Devices Inc.

-
AMC1311BDWVR
Texas Instruments

-
AMC1350DWVR
Texas Instruments

-
ADUM3190SRQZ-RL7
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

