Texas Instruments LMK03328RHSRP3

Overview

LMK03328RHSRP3 from Texas Instruments is an ultra-low-jitter clock generator with two independent fractional-N PLLs, eight programmable outputs (AC-LVPECL/LVDS/CML/HCSL/LVCMOS), integrated EEPROM for pin-selectable startup, and dual reference inputs (crystal or external 1–300 MHz). It delivers 100 fs RMS jitter (FOUT > 100 MHz) and supports PCIe Gen1–Gen6 timing in high-speed serial infrastructure.

For engineers reviewing the LMK03328RHSRP3 datasheet, LMK03328RHSRP3 pinout, LMK03328RHSRP3 application, or LMK03328RHSRP3 equivalent, this page provides verified electrical specs, validated pin functions, confirmed package mapping to 48-WQFN (7 mm × 7 mm), and real-world use cases in telecom line cards, server clock trees, and PCIe Gen5/Gen6 systems.

Technical Context

The LMK03328RHSRP3 integrates two fully independent fractional-N synthesizers with on-die VCOs (4.8–5.4 GHz), each supporting configurable R/M/N dividers, loop bandwidth tuning (up to 400 kHz), and charge pump currents up to 6.4 mA. Its Smart MUX enables automatic or manual selection between primary and secondary reference inputs (10–52 MHz crystal or 1–300 MHz external).

Output distribution includes eight differential/LVCMOS pairs with per-channel supply domains (1.8 V/2.5 V/3.3 V), programmable output formats, fine frequency margining (±50 ppm via pullable crystal), and glitchless coarse margining using output dividers. The on-chip EEPROM stores 71 pre-programmed startup configurations accessible via HW_SW_CTRL pin mode.

Key Specifications

Pinout & Package

LMK03328RHSRP3 is housed in a 7 mm × 7 mm, 48-pin WQFN (RHS) package with exposed thermal pad (DAP). The DAP must be connected to PCB ground via 6×6 array of 0.3-mm vias for optimal thermal performance (θJB = 6.84°C/W) and electrical stability.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock generator applications.

Compared with Si5341-B-GM and ICS8430I-01T, the LMK03328RHSRP3 uniquely combines EEPROM-autonomous startup, dual-PLL independence, and ±50 ppm crystal margining - making it optimal for telecom infrastructure requiring field-upgradable timing profiles and rapid power-on readiness.

Availability

LMK03328RHSRP3 is available at Aetrix Electronics and suitable for PCIe Gen6 server designs, 5G base station line cards, and broadcast IP routing systems requiring stable component supply, long-term lifecycle support, and traceable sourcing.

Supply support for LMK03328RHSRP3 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and clock solutions, with decades of expertise in high-performance timing devices for communications and computing.

The LMK03328RHSRP3 belongs to TI's LMK ultra-low-jitter clock generator family, engineered specifically for multi-gigabit serial interface timing in networking, data center, and wireless infrastructure where phase noise and deterministic jitter directly impact link reliability.

FAQ

What is the guaranteed jitter performance of the LMK03328RHSRP3 across its operating range?

The LMK03328RHSRP3 guarantees 100 fs RMS jitter (typical) for output frequencies above 100 MHz, measured over a 12 kHz to 20 MHz integration bandwidth. This value is validated per JEDEC JESD65B and aligns with PCIe Gen6 reference clock requirements. Measured phase noise floor is –164 dBc/Hz at 156.25 MHz, confirming robust high-frequency spectral purity in the LMK03328RHSRP3.

Does the LMK03328RHSRP3 support direct connection to a crystal oscillator without external components?

Yes, the LMK03328RHSRP3 supports direct connection of a fundamental-mode AT-cut crystal (10–52 MHz) to SECREF_P/SECREF_N pins. It integrates on-chip load capacitance tuning (Con-chip variation up to 1.5 pF), crystal drive-level limiting (<300 µW), and bias circuitry - eliminating external capacitors, resistors, or amplifiers required by most competing clock generators.

How many independent power domains does the LMK03328RHSRP3 provide for its outputs?

The LMK03328RHSRP3 provides seven independent output power domains: VDDO_01 (OUT0/OUT1), VDDO_23 (OUT2/OUT3), VDDO_4 (OUT4), VDDO_5 (OUT5), VDDO_6 (OUT6), VDDO_7 (OUT7), plus VDD_DIG for digital control. Each domain accepts 1.8 V, 2.5 V, or 3.3 V, enabling mixed-voltage clock distribution without external level shifters in the LMK03328RHSRP3.

Can the LMK03328RHSRP3 generate PCIe Gen6 REFCLK without external filtering or conditioning?

Yes, the LMK03328RHSRP3 generates PCIe Gen6-compliant 100 MHz REFCLK directly from its AC-LVPECL outputs with 100 fs RMS jitter and –164 dBc/Hz phase noise floor at 156.25 MHz. Its –80 dBc PSNR rejects board-level supply noise, and integrated loop filters (LF1/LF2) eliminate need for external passive components - full compliance is achieved within the LMK03328RHSRP3.

What configuration modes does the LMK03328RHSRP3 support, and how are they selected?

The LMK03328RHSRP3 supports three configuration modes: Hard Pin Mode (ROM), EEPROM Mode, and Register Default Mode - selected via the HW_SW_CTRL pin. EEPROM Mode loads one of 71 pre-programmed startup states on power-up, enabling field-upgradable timing profiles without host processor intervention - a key differentiator of the LMK03328RHSRP3.