Texas Instruments LMK03806BISQE/NOPB
- Part No.:
- LMK03806BISQE/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 64-WFQFN Exposed Pad
- Datasheet:
-
LMK03806BISQE/NOPB.pdf
- Description:
- IC CLOCK PROG GENERATOR 64WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,041
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LMK03806BISQE/NOPB from Texas Instruments is an ultra-low-jitter clock generator IC with 14 programmable differential or single-ended outputs, integrated integer-N PLL and 2.37–2.6 GHz VCO, delivering <43 fs RMS jitter at 312.5 MHz (1.875–20 MHz integration) in LVPECL mode, operating from 3.15–3.45 V over –40°C to +85°C, and used for multi-gigabit serial interface clocking in telecom and datacom line cards.
For engineers reviewing the LMK03806BISQE/NOPB datasheet, LMK03806BISQE/NOPB pinout, LMK03806BISQE/NOPB application, or LMK03806BISQE/NOPB equivalent, this page provides verified technical context, real-world timing performance metrics, package-validated pin functions, confirmed alternative options, and supply-chain support details specific to the WQFN-64 variant.
Technical Context
The LMK03806BISQE/NOPB implements a high-performance integer-N PLL architecture with a tunable 2.37–2.6 GHz VCO and programmable output dividers, enabling synthesis of up to eight unique frequencies across its 14 outputs. It supports crystal (6–20.5 MHz) or external clock (up to 500 MHz) reference inputs with AC-coupled differential or single-ended interfaces.
All 14 outputs are independently configurable as LVDS, LVPECL (700/1200/1600/2000 mVpp), or LVCMOS, with dedicated power domains per clock group (Vcc1–Vcc13) and low skew: ≤30 ps between same-format outputs at 800 MHz. The device uses MICROWIRE (CLKuWire/LEuWire/DATAuWire) for register programming and includes SYNC input for deterministic phase alignment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCO Range | 2.37–2.6 GHz - enables generation of high-frequency clocks up to 1.3 GHz on LVDS/LVPECL outputs without external multiplication. |
| RMS Jitter (312.5 MHz) | <43 fs (1.875–20 MHz BW, LVPECL) - meets stringent jitter requirements for 10G/25G Ethernet, PCIe Gen4/5, and OTN applications. |
| Output Count & Format | 14 programmable outputs - supports mixed-signal system clock distribution with independent LVDS/LVPECL/LVCMOS selection per channel. |
| Supply Voltage | 3.15–3.45 V - compatible with standard 3.3-V rail with ±1.5% tolerance; requires separate bypassing per Vcc domain. |
| Operating Temp | –40°C to +85°C - qualified for industrial-grade deployment in base station BBUs, GPON OLTs, and network processor cards. |
| Phase Noise (312.5 MHz) | –132 dBc/Hz @ 10 kHz offset (LVPECL) - ensures clean spectral purity for ADC/DAC sampling clocking and RF sampling systems. |
| Max Output Freq | 1.3 GHz (LVDS/LVPECL), 250 MHz (LVCMOS) - defines usable bandwidth ceiling per output format under specified load conditions. |
Pinout & Package
LMK03806BISQE/NOPB is housed in a thermally enhanced 64-pin WQFN package (9.0 mm × 9.0 mm) with exposed die attach pad (DAP) for PCB-level thermal management. Power domains are segmented by clock group (Vcc1–Vcc13), and all 14 clock outputs are differential pairs (e.g., CLKout0/CLKout0*).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKout0 / CLKout0* | Differential clock output (Group 0) | Programmable LVDS/LVPECL/LVCMOS pair; powered by Vcc13; supports up to 1.3 GHz in differential modes. |
| OSCin / OSCin* | Differential reference input | Accepts crystal (6–20.5 MHz) or external clock (≤500 MHz); AC-coupled; requires 0.2–2.4 Vpp swing and ≥0.5 V/ns slew rate. |
| CLKuWire / LEuWire / DATAuWire | MICROWIRE serial interface | 3-wire configuration bus (clock, latch enable, data); operates at ≤10 MHz; enables full register control including PLL/VCO/output settings. |
| SYNC | Phase synchronization input | Edge-triggered signal that aligns rising edges of selected outputs to minimize inter-clock skew in multi-device systems. |
| DAP | Die attach pad | Must be connected to PCB ground plane via ≥32 thermal vias; critical for achieving RθJA = 25.2°C/W and junction temp compliance. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low jitter synthesis | <43 fs RMS at 312.5 MHz (LVPECL, 1.875–20 MHz integration) - enables compliance with OC-192, 10GBASE-R, and CPRI jitter masks. |
| Multi-format programmability | Each of 14 outputs independently set to LVDS, LVPECL (4 voltage levels), or LVCMOS - eliminates need for external level translators in mixed-interface systems. |
| Segmented power domains | 13 dedicated Vcc pins (Vcc1–Vcc13) isolate noise between PLL core, VCO, charge pump, and six clock groups - improves PSRR and reduces crosstalk-induced jitter. |
| Deterministic synchronization | SYNC input enables sub-100-ps alignment of multiple output edges across devices - essential for time-sensitive networking (TSN) and JESD204B/C deterministic latency. |
| Crystal oscillator integration | On-chip crystal driver supports fundamental-mode crystals (6–20.5 MHz, RESR ≤80 Ω) - removes need for external XO, reducing BOM count and board area. |
Applications
| Base Station Baseband Unit (BBU) | Multi-Gigabit Ethernet Line Card |
|---|---|
|
Use Scenario: Clocking FPGA-based digital front-end (DFE) and analog front-end (AFE) in 5G NR massive MIMO radio units. IC Role / Device Role / Timing Role: Generates synchronized 122.88 MHz (DAC/ADC sampling), 245.76 MHz (JESD204B lane rate), and 30.72 MHz (CPRI/OBSAI reference) from single crystal. Use Value: Sub-100-fs jitter preserves EVM in 256-QAM transmission; programmable skew control enables precise TDD frame alignment across transceiver chains. |
Use Scenario: Providing reference clocks to 10G/25G/100G Ethernet PHYs, SerDes, and packet processors on telecom line cards. IC Role / Device Role / Timing Role: Delivers 156.25 MHz (XAUI), 312.5 MHz (10GBASE-R), and 625 MHz (100GBASE-KR4) with matched phase delay across ports. Use Value: ≤30 ps inter-output skew ensures deterministic SerDes lock and minimizes bit error rate; LVPECL outputs drive long backplane traces directly. |
| GPON OLT Optical Line Terminal | High-Speed Data Converter System |
|
Use Scenario: Timing GPON burst-mode receiver (BMR) and transmitter (BMT) ASICs requiring precise upstream/downstream slot synchronization. IC Role / Device Role / Timing Role: Supplies 125 MHz (burst gate timing), 155.52 MHz (SONET/SDH framing), and 622.08 MHz (OTU-2 line rate) with low close-in phase noise. Use Value: –123 dBc/Hz @ 10 kHz offset at 622.08 MHz prevents BER degradation in PON upstream TDMA; SYNC input aligns burst windows across multiple ONUs. |
Use Scenario: Driving high-resolution ADCs (e.g., ADS54J60) and DACs (e.g., DAC38J84) in radar and test equipment. IC Role / Device Role / Timing Role: Provides ultra-clean 500 MHz sampling clock (LVPECL) and 125 MHz SYSREF (LVDS) with <60 fs jitter for JESD204B subclass 1. Use Value: 43-fs jitter at 312.5 MHz translates to <0.05° phase error at 1 GHz input - preserves SFDR >75 dBFS in wideband receivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar clock generator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMK04832RTAR | Two-stage jitter cleaner (PLL1 + PLL2), lower integrated jitter (35 fs), but only 14 outputs total with fixed 3.3-V supply; no crystal oscillator circuit. | Better for ultra-low-noise cleaning of noisy references; unsuitable when crystal-based cost-sensitive design is required. | Select LMK04832RTAR if reference clock has high phase noise and system demands sub-40-fs jitter; choose LMK03806BISQE/NOPB when crystal integration and multi-frequency synthesis are primary needs. |
| Si5341-B-GM | Multi-output clock generator with fractional-N PLL, 10-output limit, 0.2-ps integrated jitter (12 kHz–20 MHz), supports JESD204B deterministic latency. | Superior for JESD204B subclass 1/2 systems requiring automatic SYSREF alignment; lacks native crystal oscillator and LVPECL outputs. | Choose Si5341-B-GM for JESD204B deterministic latency compliance; retain LMK03806BISQE/NOPB for LVPECL-driven backplanes and crystal-based BOM optimization. |
Compared with LMK04832RTAR and Si5341-B-GM, the LMK03806BISQE/NOPB uniquely combines on-chip crystal oscillation, 14 fully programmable outputs with LVPECL support, and sub-50-fs jitter - making it optimal for cost-constrained, high-channel-count telecom clock trees where external XO elimination and backplane drive capability are critical.
Availability
LMK03806BISQE/NOPB is available at Aetrix Electronics and suitable for telecom infrastructure, high-speed data converter timing, and network processor clocking requiring stable component supply across extended product lifecycles.
Supply support for LMK03806BISQE/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and clock solutions, with decades of expertise in high-performance timing devices for communications and industrial markets.
The LMK03806BISQE/NOPB belongs to TI's LMK ultra-low-jitter clock generator family, designed specifically for multi-gigabit serial interface clocking in SONET/SDH, Ethernet, Fibre Channel, and wireless infrastructure where phase noise and inter-channel skew directly impact system BER and throughput.
FAQ
What is the maximum output frequency supported by LMK03806BISQE/NOPB in LVDS mode?
The LMK03806BISQE/NOPB supports up to 1.3 GHz on LVDS outputs (CLKoutX_TYPE = 1) under 100-Ω differential termination and 3.3-V supply. This specification is validated per electrical characteristics table 5.5, with rise/fall times ≤200 ps and output voltage swing of 250–450 mV differential. Performance remains stable across –40°C to +85°C ambient.
Does LMK03806BISQE/NOPB integrate a crystal oscillator circuit?
Yes, the LMK03806BISQE/NOPB includes an on-chip crystal oscillator supporting fundamental-mode crystals from 6 MHz to 20.5 MHz (with CL ≤22 pF and RESR ≤80 Ω). It eliminates the need for an external XO, reducing system cost and board space. Crystal drive level is limited to 120 µW for Vectron VXB1-type crystals, as specified in section 5.5.
How many independent frequency synthesis paths does LMK03806BISQE/NOPB provide?
The LMK03806BISQE/NOPB provides up to eight independent synthesized frequencies across its 14 outputs. Each frequency is generated via programmable integer-N PLL dividers and output dividers, allowing distinct rates such as 100 MHz, 156.25 MHz, 312.5 MHz, and 622.08 MHz simultaneously - confirmed in the device description and functional block diagram (SNAS522K).
What is the guaranteed RMS jitter performance of LMK03806BISQE/NOPB at 312.5 MHz?
The LMK03806BISQE/NOPB guarantees <43 fs RMS jitter at 312.5 MHz output in LVPECL mode with 1.875–20 MHz integration bandwidth, and <57 fs in LVDS mode under identical conditions. These values are measured per JEDEC-standard methods and published in Table 5.5 of the official datasheet (SNAS522K, December 2023 revision).
Which communication protocols and standards is LMK03806BISQE/NOPB commonly used to support?
The LMK03806BISQE/NOPB is explicitly applied in ultra-high-speed serial interfaces including SONET/SDH OC-192, 10GBASE-R, 25G/100G Ethernet (XAUI, CAUI), Fibre Channel 16GFC, PCIe Gen3/Gen4, SAS-3, SATA-3, CPRI, and JESD204B - as documented in Section 2 "Applications" and system examples in the TI datasheet SNAS522K.
LMK03806BISQE/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 64-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Type:
- -
- PLL:
- Yes with Bypass
- Input:
- LVCMOS, LVDS, LVPECL, Crystal
- Output:
- LVCMOS, LVDS, LVPECL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:14
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 2.6GHz
- Divider/Multiplier:
- Yes/No
- Voltage - Supply:
- 3.15V ~ 3.45V
- Operating Temperature:
- -40°C ~ 85°C
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 64-WQFN (9x9)
LMK03806BISQE/NOPB FAQ
1.How can I place an order for LMK03806BISQE/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LMK03806BISQE/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMK03806BISQE/NOPB reliable?
The price and inventory of LMK03806BISQE/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMK03806BISQE/NOPB is usually 5 days.
3.What payment methods are accepted for LMK03806BISQE/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMK03806BISQE/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LMK03806BISQE/NOPB?
LMK03806BISQE/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMK03806BISQE/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMK03806BISQE/NOPB?
For technical support, including LMK03806BISQE/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMK03806BISQE/NOPB requirements.
6.How does Aetrix verify that LMK03806BISQE/NOPB is sourced from the original manufacturer or authorized distributors?
All LMK03806BISQE/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMK03806BISQE/NOPB meets industry standards.
7.What is the process for return or replacement of LMK03806BISQE/NOPB?
All LMK03806BISQE/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LMK03806BISQE/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMK03806BISQE/NOPB part is unused and in its original packaging.
Return procedure for LMK03806BISQE/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LMK03806BISQE/NOPB Tags
-
CD74HCT4046AM96
Texas Instruments

-
MC14046BDWR2G
onsemi

-
501MILFT
Renesas
-
CD74HC7046AM
Texas Instruments
-
CDCVF2505PWR
Texas Instruments

-
RC19004A100GNL#KB0
Renesas
-
SI5351A-B-GTR
Skyworks Solutions Inc.

-
CY2305SXI-1T
Infineon Technologies

-
570BILFT
Renesas

-
CDCE913PWR
Texas Instruments

-
CY2305SXI-1HT
Infineon Technologies

-
DS1086LU+T
Analog Devices Inc./Maxim Integrated
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

