Texas Instruments LMK04228NKDR

Overview

LMK04228 from Texas Instruments is an ultra-low-noise, JESD204B-compliant clock jitter cleaner with dual-loop PLL architecture. It delivers up to 14 differential device clocks and 7 SYSREF outputs at frequencies up to 1.25 GHz, featuring 156 fs RMS jitter (12 kHz–20 MHz), –224 dBc/Hz normalized PLL2 noise floor, and dual VCOs (2370–2630 MHz and 2920–3080 MHz). It serves as a high-performance clock conditioner for data converter synchronization in wireless infrastructure and test equipment.

For engineers reviewing the LMK04228 datasheet, LMK04228 pinout, LMK04228 application, or LMK04228 equivalent, key selection considerations include JESD204B SYSREF timing precision, dual-PLL holdover capability during reference loss, programmable LVPECL/LVDS/LVCMOS output formats, and per-output 25-ps analog delay with digital delay support.

Technical Context

The LMK04228 implements a dual-loop PLLatinum™ architecture: PLL1 accepts up to three redundant input clocks (CLKin0/1/2), supports hitless switching, LOS detection, and holdover via integrated crystal oscillator circuitry; PLL2 uses two independent low-noise VCOs and achieves a normalized 1-Hz phase noise floor of –224 dBc/Hz with phase detector rates up to 155 MHz.

It provides 14 programmable differential clock outputs (DCLKout0–12*, SDCLKout1–13*) configurable as device clocks or SYSREF signals, with 50% duty-cycle dividers (1–32, odd/even), precision digital delay, and 25-ps step analog delay per output - enabling sub-picosecond alignment critical for multi-ADC/DAC JESD204B systems.

Key Specifications

Pinout & Package

Package: 64-pin WQFN (9.0 mm × 9.0 mm × 0.8 mm) with exposed thermal pad (DAP), optimized for low-jitter PCB layout and thermal dissipation in dense clock distribution systems.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar clock jitter cleaner applications.

Compared with LMK04832 and AD9545, the LMK04228 offers the optimal balance of JESD204B-specific features (7 SYSREF outputs, 25-ps analog delay), compact 64-pin WQFN packaging, and lowest power consumption among TI's jitter cleaners - making it the preferred choice for embedded converter clocking where board area and thermal envelope are constrained.

Availability

LMK04228 is available at Aetrix Electronics and suitable for wireless infrastructure, data converter clocking, and test and measurement applications requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.

Supply support for LMK04228 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance signal chain solutions, with decades of leadership in precision timing and clock management ICs.

The LMK04228 belongs to TI's PLLatinum™ clock jitter cleaner product line, engineered specifically for JESD204B-compliant data converter systems demanding ultra-low jitter, deterministic SYSREF, and robust reference redundancy in industrial and communications environments.

FAQ

What is the maximum supported input frequency for the LMK04228 reference inputs?

The LMK04228 supports reference input frequencies from 1 kHz up to 400 MHz on its CLKin0/1/2 ports. The OSCin port accepts up to 500 MHz (characterized) or 155 MHz when the frequency doubler is enabled. These ranges allow compatibility with common crystal oscillators, TCXOs, and recovered system clocks while maintaining optimal phase noise performance.

Does the LMK04228 support both AC- and DC-coupled SYSREF outputs?

Yes, the LMK04228 supports both AC- and DC-coupled SYSREF outputs via its SDCLKoutx pins. Configuration is performed through register settings controlling output stage biasing and coupling mode - enabling seamless integration with JESD204B subclass 1 (DC-coupled) and subclass 2 (AC-coupled) receiver implementations without external components.

How does the LMK04228 handle reference clock failure?

The LMK04228 implements automatic hitless switching between up to three redundant reference inputs (CLKin0/1/2) and enters holdover mode using its integrated low-noise crystal oscillator circuit when all references are lost. Holdover maintains output stability within ±0.1 ppm drift over 24 hours, preserving system timing integrity during transient reference outages.

Can the LMK04228 generate both device clocks and SYSREF signals simultaneously?

Yes, the LMK04228 generates up to 14 differential clock outputs, configurable as either device clocks (DCLKoutx) or SYSREF signals (SDCLKoutx). Seven of these outputs are designated for SYSREF use, and all support independent programming of format (LVPECL/LVDS/LVCMOS), frequency, phase, and delay - enabling concurrent high-fidelity device clocking and deterministic multi-converter synchronization.

What is the significance of the –224 dBc/Hz normalized phase noise specification for the LMK04228?

The –224 dBc/Hz normalized phase noise at 1 Hz offset quantifies the intrinsic noise contribution of PLL2's synthesizer core. This ultra-low value minimizes in-band phase noise degradation in cascaded clock trees, directly translating to lower jitter accumulation and improved SNR in high-speed data converters - especially critical for wideband RF sampling applications above 1 GHz.