Texas Instruments LMK05028RGCR

Overview

LMK05028RGCR from Texas Instruments is a dual-channel network synchronizer IC designed for telecom and industrial timing systems, delivering 150 fs RMS jitter (≥100 MHz), hitless switching with ≤50 ps phase transient, and IEEE 1588 PTP slave DCO mode (<1 ppt/step). It supports SyncE (G.8262), Stratum 3E, and optical transport timing in line cards and timing cards.

For engineers reviewing the LMK05028RGCR datasheet, LMK05028RGCR pinout, LMK05028RGCR application, or LMK05028RGCR equivalent, this page provides verified specifications, validated VQFN-64 pin functions, confirmed dual-PLL architecture with TCXO/OCXO holdover, and two field-deployed alternative options for network synchronizer replacement.

Technical Context

The LMK05028RGCR integrates two independent all-digital PLLs (DPLL1/DPLL2) and two analog PLLs (APLL1/APLL2), each with dedicated VCOs (4.8–5.4 GHz and 5.5–6.2 GHz), enabling simultaneous jitter cleaning and frequency translation across eight programmable outputs. Input selection supports priority-based switching among four differential reference inputs (IN0–IN3), plus XO and TCXO_IN inputs.

It implements deterministic zero-delay phase offset, digital holdover on reference loss, and EEPROM-based power-up configuration. Output drivers support AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8/2.5-V LVCMOS formats across two output banks-OUT[0:3] optimized for PLL2 and OUT[4:7] for PLL1-to minimize crosstalk.

Key Specifications

Pinout & Package

The LMK05028RGCR is housed in a 64-pin VQFN package (RGC), 9.0 mm × 9.0 mm, with exposed thermal pad requiring 7×7 via pattern to PCB ground for thermal and electrical integrity.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar network synchronizer applications.

Compared with LMK05028RGCR, the LMK05318RHBR reduces channel count but improves DCO granularity and integration, while the Si5342-D06984-GM trades dual-PLL flexibility for lower jitter and crystal integration-making LMK05028RGCR optimal for carrier-grade dual-domain timing where redundancy and EEPROM-based startup are critical.

Availability

LMK05028RGCR is available at Aetrix Electronics and suitable for SyncE timing cards, IEEE 1588 PTP slave modules, and optical transport network equipment requiring stable component supply, long-term lifecycle assurance, and traceable sourcing for carrier infrastructure deployments.

Supply support for LMK05028RGCR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and timing solutions, with decades of expertise in high-reliability communications infrastructure ICs.

The LMK05028RGCR belongs to TI's LMK family of network synchronizers, engineered specifically for carrier-grade timing applications demanding G.8262 compliance, hitless switchover, and deterministic phase control in 5G, OTN, and enterprise networking systems.

FAQ

What is the primary timing function of the LMK05028RGCR?

The LMK05028RGCR serves as a dual-channel network synchronizer IC that performs jitter cleaning, frequency translation, and phase-locked synchronization for telecom infrastructure. Its core function is to generate ultra-low-jitter clocks (150 fs RMS) from noisy or unstable references while supporting hitless switching and IEEE 1588 DCO mode. The LMK05028RGCR achieves this using two independent DPLL+APLL domains, enabling simultaneous SyncE and PTP timing in a single device.

Does the LMK05028RGCR support both I²C and SPI interfaces?

Yes, the LMK05028RGCR supports both I²C and SPI serial interfaces, selected at power-on via the HW_SW_CTRL pin. When HW_SW_CTRL = 0, it defaults to I²C with open-drain SDA/SCL requiring external pullups; when floating (biased to ~0.8 V), it enables SPI mode with SDI/SCK/SCS/SDO signals. The LMK05028RGCR retains full register access and configuration capability under either protocol, including EEPROM programming and real-time status monitoring.

How does the LMK05028RGCR implement holdover during reference loss?

The LMK05028RGCR implements digital holdover by locking its DPLLs to a stable TCXO or OCXO connected to the TCXO_IN pin. Upon loss of all four primary reference inputs (IN0–IN3), the device seamlessly transitions to holdover mode using the TCXO as the timing source, maintaining frequency accuracy within ±0.1 ppm over temperature. This behavior is standards-compliant for G.8262 and Stratum 3E applications. The LMK05028RGCR monitors reference status continuously and reports holdover entry/exit via STATUS0/STATUS1 pins.

What output voltage levels and formats does the LMK05028RGCR support?

The LMK05028RGCR supports eight programmable clock outputs with selectable drive formats: AC-LVDS, AC-CML, AC-LVPECL, HCSL, and 1.8 V or 2.5 V LVCMOS. Output supply voltages (VDDO_x) are independently configurable per bank-1.8 V or 2.5 V for LVCMOS, and 1.8/2.5/3.3 V for differential formats. Each output pair can be individually enabled/disabled and assigned to PLL1 or PLL2 domains. The LMK05028RGCR delivers specified performance (e.g., 150 fs jitter, –162 dBc/Hz phase noise) only when configured per recommended operating conditions in the datasheet.

Can the LMK05028RGCR generate different frequencies on its eight outputs simultaneously?

Yes, the LMK05028RGCR can generate up to six distinct output frequencies simultaneously across its eight outputs. Each output is driven by a post-divider with programmable division ratio, and outputs are grouped into two banks-OUT[0:3] sourced from PLL2 and OUT[4:7] from PLL1-allowing independent frequency synthesis per domain. The LMK05028RGCR supports any-input-to-any-output frequency translation, including fractional-N synthesis, and stores custom configurations in on-chip EEPROM for automatic power-up initialization without host intervention.