Texas Instruments LMK61E2-125M00SIAR

Overview

LMK61E2-125M00SIAR from Texas Instruments is an ultra-low-jitter LVPECL oscillator generating a precise 125 MHz reference clock for high-speed serial interfaces. It delivers 90 fs RMS jitter (typical, >100 MHz), ±50 ppm total frequency tolerance, and operates from a single 3.3 V supply across –40°C to +85°C. Its primary role is timing reference generation in FPGA/ASIC clock trees requiring sub-100-fs jitter performance.

For engineers reviewing the LMK61E2-125M00SIAR datasheet, LMK61E2-125M00SIAR pinout, LMK61E2-125M00SIAR application, or LMK61E2-125M00SIAR equivalent, key selection criteria include differential output format compatibility (LVPECL), PSRR (–70 dBc), startup time (10 ms), OE control latency (50 µs), and 7 mm × 5 mm QFM package footprint alignment with industry-standard 7050 XO footprints.

Technical Context

The LMK61E2-125M00SIAR integrates a high-stability PLL-based core with internal power conditioning to achieve robust supply noise immunity. Its LVPECL output stage supports up to 1 GHz operation with 700–1200 mV differential swing and 120–200 ps rise/fall times (20%–80%).

It features an LVCMOS OE input with internal pull-up, enabling hardware-controlled output disable into high-impedance state. The device is factory-programmed for fixed 125 MHz LVPECL output and does not support frequency reconfiguration in-system.

Key Specifications

Pinout & Package

LMK61E2-125M00SIAR uses a 6-pin QFM (7.0 mm × 5.0 mm) surface-mount package, pin-compatible with standard 7050 XO footprints. Thermal vias under the GND pad are required for junction temperature control.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar ultra-low-jitter oscillator applications.

Compared with LMK61E2-125M00SIAR, the SIAT variant offers identical performance in tape-and-reel form for production lines, while the Si510 provides tighter stability and lower jitter but requires LVDS interface redesign and PCB rework due to non-pin-compatible 5×3.2 mm QFN.

Availability

LMK61E2-125M00SIAR is available at Aetrix Electronics and suitable for 10G/25G Ethernet PHY clocking, FPGA transceiver reference, and PCIe Gen4/Gen5 root complex timing requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.

Supply support for LMK61E2-125M00SIAR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog, embedded processing, and clock solutions, with leadership in high-performance timing ICs and signal chain components.

The LMK61XX family was designed specifically for replacing quartz oscillators in high-speed digital systems where ultra-low jitter, supply noise immunity, and programmable output formats are critical - targeting networking, computing, and test equipment markets.

FAQ

What output format does the LMK61E2-125M00SIAR support?

The LMK61E2-125M00SIAR is factory-programmed for LVPECL output only. It does not support LVDS or HCSL modes. Its differential LVPECL outputs (OUTP/OUTN) require termination to VDD − 2 V and deliver 700–1200 mV swing at 125 MHz. This fixed configuration is confirmed in TI's SNAS676D datasheet Table "Device Information" and Pin Functions section.

Is the LMK61E2-125M00SIAR pin-compatible with standard 7050 crystal oscillator footprints?

Yes, the LMK61E2-125M00SIAR uses a 6-pin QFM package measuring 7.0 mm × 5.0 mm, explicitly stated as pin-compatible with industry-standard 7050 XO packages. Pin 1 (OE) maps to the same location as typical XO ST/EN pins, and GND (pin 3) and VDD (pin 6) align with common power pin placements - enabling drop-in replacement without PCB redesign.

What is the maximum allowable power supply ripple for the LMK61E2-125M00SIAR?

The LMK61E2-125M00SIAR maintains –70 dBc PSRR across 50 kHz to 1 MHz, meaning it suppresses 50 mVpp sinusoidal ripple on VDD to <50 µVpp at the output. This allows operation with switching regulator outputs without additional filtering, provided ripple amplitude stays below 50 mVpp - verified in Section 6.12 of the SNAS676D datasheet.

Does the LMK61E2-125M00SIAR support frequency adjustment after programming?

No, the LMK61E2-125M00SIAR is factory-programmed for fixed 125 MHz LVPECL output and contains no I²C, SPI, or pin-strapping interface for reconfiguration. Unlike programmable variants (e.g., LMK61E0 series), it lacks internal NVM or external control for frequency tuning - confirmed by its "E2" suffix denoting fixed-frequency, ±50 ppm grade in TI's LMK61XX family documentation.

How does the OE pin function on the LMK61E2-125M00SIAR?

The OE (Output Enable) pin on the LMK61E2-125M00SIAR is an LVCMOS input with internal pull-up. When held high or floating, outputs are active; when pulled low (<0.6 V), both OUTP and OUTN enter high-impedance state within 50 µs. This enables dynamic clock gating in power-managed systems - detailed in Section 6.9 (OE Input Characteristics) of the SNAS676D datasheet.