Texas Instruments LMK6DA15625ADLET

Overview

LMK6DA15625ADLET from Texas Instruments is a fixed-frequency, ultra-low-jitter BAW-based LVDS oscillator delivering 156.25 MHz output with ±25 ppm total frequency stability over –40°C to 85°C, 2.5V–3.3V supply, and 100 fs typical RMS jitter (12 kHz–20 MHz). It serves as a PCIe Gen 7–compliant reference clock in high-speed SERDES for optical transport and data center switches.

For engineers reviewing the LMK6DA15625ADLET datasheet, LMK6DA15625ADLET pinout, LMK6DA15625ADLET application, or LMK6DA15625ADLET equivalent, key selection criteria include LVDS output compliance, sub-125 fs jitter at 156.25 MHz, DLE 3.2 mm × 2.5 mm package footprint, standby functionality on Pin 1, and integrated LDO for supply noise immunity.

Technical Context

The LMK6DA15625ADLET implements TI's Bulk-Acoustic Wave (BAW) resonator technology directly integrated into the package, eliminating external crystal dependencies and enabling mechanical robustness and fast start-up (<5 ms). Its fractional output divider is factory-programmed for exact 156.25 MHz generation without external configuration.

It uses a dedicated LVDS output driver with differential swing of 250–450 mV under load, common-mode voltage of 1.025–1.375 V at 2.5V/3.3V, and supports active-low standby control on Pin 1 - disabling output while drawing only 6–13 mA quiescent current.

Key Specifications

Pinout & Package

VSON package DLE-6 (3.2 mm × 2.5 mm, 6-pin), moisture sensitivity level MSL1, suitable for reflow soldering per JEDEC J-STD-020.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar oscillator applications.

Compared with LMK6DA15625ADLET, LMK6D0I15625ADLET offers identical electrical performance but alternate pin assignment for standby control, whereas Si510-156M250-100 trades LVDS noise immunity and ultra-low jitter for lower cost and CMOS compatibility - limiting its use to non-critical clock trees.

Availability

LMK6DA15625ADLET is available at Aetrix Electronics and suitable for 100G/400G optical transport, PCIe Gen 7 server platforms, and high-density data center switches requiring stable component supply, guaranteed long-term availability, and traceable sourcing.

Supply support for LMK6DA15625ADLET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in precision timing, power management, and signal chain solutions.

The LMK6x product line delivers ultra-low-jitter, BAW-based oscillators designed specifically for high-speed serial interface timing in telecom infrastructure, enterprise networking, and AI/ML hardware - replacing legacy crystal+buffer solutions with integrated, robust alternatives.

FAQ

What is the output type and interface standard supported by LMK6DA15625ADLET?

The LMK6DA15625ADLET provides a differential LVDS output compliant with ANSI TIA/EIA-644-A. It delivers 156.25 MHz at 250–450 mV peak-to-peak swing, 1.025–1.375 V common-mode voltage, and supports termination into 100 Ω differential loads. This makes LMK6DA15625ADLET suitable for direct connection to SerDes receivers requiring LVDS-level clocks.

Does LMK6DA15625ADLET support PCIe Gen 7 timing requirements?

Yes, LMK6DA15625ADLET meets PCIe Gen 7 common-clock jitter specification (≤67 fs peak-to-peak) with measured 100 fs typical RMS jitter (12 kHz–20 MHz) at 156.25 MHz. Its phase noise profile (–156.5 dBc/Hz at 10 MHz offset) and validated PCIe jitter metrics confirm compliance across all Gen 1–7 generations without external cleanup circuitry.

What is the function of Pin 1 on LMK6DA15625ADLET, and how is it used?

Pin 1 on LMK6DA15625ADLET is the Standby (ST) input, active-low. When pulled to GND, it disables the LVDS output drivers and reduces current consumption to 6–13 mA. When left floating or pulled high (via pull-up), the device operates normally. This feature enables dynamic power gating in systems requiring low-quiescent states between traffic bursts.

What package type and dimensions does LMK6DA15625ADLET use?

LMK6DA15625ADLET uses the VSON DLE-6 package: 3.2 mm × 2.5 mm footprint, 0.5 mm pitch, 6-pin configuration, and MSL1 moisture sensitivity rating. Its compact size supports high-density placement adjacent to FPGA/ASIC SerDes banks, and the exposed pad variant improves thermal dissipation in thermally constrained line cards.

How does the BAW resonator in LMK6DA15625ADLET improve reliability versus quartz crystal solutions?

The BAW resonator in LMK6DA15625ADLET is monolithically integrated within the silicon die and package, eliminating bond wires, ceramic enclosures, and external load capacitors. This architecture achieves superior shock/vibration resistance (1500 g mechanical shock), eliminates aging-related frequency drift beyond 10 years, and removes crystal start-up failures - resulting in higher field reliability in telecom and industrial environments.