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Texas Instruments LMK6DA15625ADLFT
- Part No.:
- LMK6DA15625ADLFT
- Manufacturer:
- Texas Instruments
- Category:
- Oscillators
- Package:
- 6-VDFN
- Datasheet:
-
LMK6DA15625ADLFT.pdf
- Description:
- BAW OSC LVDS 3.3V 156MHZ 6 PIN
- Quantity:
- Payment:
- Shipping:
Inventory:2,070
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Product details
Overview
LMK6DA15625ADLFT from Texas Instruments is a factory-programmed, ultra-low-jitter BAW-based LVDS oscillator delivering 156.25 MHz output with ±25 ppm total frequency stability, 100 fs typical RMS jitter (12 kHz–20 MHz), and operation across 2.5V–3.3V supply at –40°C to +85°C - deployed as a reference clock in 100G/400G optical transport and PCIe Gen 7 systems.
For engineers reviewing the LMK6DA15625ADLFT datasheet, LMK6DA15625ADLFT pinout, LMK6DA15625ADLFT application, or LMK6DA15625ADLFT equivalent, key selection criteria include its DLF package (2.5 mm × 2.0 mm), Pin 1 Standby (active low) control, LVDS differential drive compliance, and guaranteed jitter performance at 156.25 MHz for high-speed SERDES timing integrity.
Technical Context
The LMK6DA15625ADLFT integrates a Bulk-Acoustic Wave (BAW) resonator directly into its VSON package, eliminating external crystal dependencies and enabling single-chip, fixed-frequency clock generation with mechanical robustness. Its fractional divider architecture supports precise 156.25 MHz synthesis without external PLL components.
It features an integrated LDO delivering –72 dBc PSRR at 500 kHz ripple, ensuring immunity to supply noise in dense PCB environments. The device enters standby mode (<13 mA ICC) when Pin 1 is pulled low, with <5 ms startup time and sub-µs output disable latency.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Frequency | 156.25 MHz - precisely factory-programmed; meets IEEE 802.3ba/100GBASE-KR and PCIe Gen 7 common-clock jitter limits. |
| RMS Jitter (12 kHz–20 MHz) | 100 fs typical / 125 fs max - enables reliable sampling margin in 56G/112G PAM4 receivers and high-speed ADCs. |
| Frequency Stability | ±25 ppm total - includes aging over 10 years, temperature drift (–40°C to +85°C), and voltage variation (±5% on 2.5V/3.3V). |
| Output Type | LVDS - delivers 250–450 mV differential swing into 100 Ω load; supports point-to-point or multi-drop routing with controlled impedance. |
| Supply Voltage | 2.5V–3.3V ±5% - dual-voltage compatibility simplifies integration into mixed-supply FPGA/ASIC platforms. |
| Package | DLF (VSON-6) - 2.5 mm × 2.0 mm footprint with 0.4 mm pitch; optimized for space-constrained optical module and switch ASIC designs. |
| Standby Control | Pin 1 active-low ST - reduces current to ≤13 mA while preserving state; enables dynamic power gating in network line cards. |
Pinout & Package
LMK6DA15625ADLFT uses a 6-pin VSON (DLF) package measuring 2.5 mm × 2.0 mm with 0.4 mm pitch. Pin 1 is dedicated to Standby (active low); pins 4 and 5 provide complementary LVDS outputs; pin 6 supplies VDD; pin 3 is GND; pin 2 is no-connect (NC) per variant configuration.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Standby (ST) | Active-low enable: pulling low disables output and reduces ICC to ≤13 mA; must be tied high or controlled via GPIO for normal operation. |
| 2 | No Connect (NC) | Not bonded; left floating per LMK6D variant specification - no routing or termination required. |
| 3 | GND | Primary ground reference; requires low-inductance connection to system ground plane for jitter minimization. |
| 4 | OUTP | Positive LVDS output; routed differentially with matched length/impedance to OUTN (pin 5) to maintain <0.1 ps skew. |
| 5 | OUTN | Negative LVDS output; forms 100 Ω differential pair with OUTP (pin 4); AC-coupled via 0.1 µF capacitors in most implementations. |
| 6 | VDD | Power input (2.5V–3.3V); requires local 100 nF + 10 µF decoupling adjacent to pin for PSRR optimization. |
Key Features
| Feature | Design Value |
|---|---|
| BAW resonator integration | Eliminates external crystal and load capacitors - reduces BOM count and board area by >30% vs discrete XO solutions. |
| Ultra-low jitter at 156.25 MHz | 100 fs typical RMS (12 kHz–20 MHz) - meets PCIe Gen 7 SRNS jitter limit (67 fs) with 1.5× design margin. |
| Integrated LDO with –72 dBc PSRR | Rejects 500 kHz supply ripple without external regulators - enables direct connection to noisy SoC/FPGA rails. |
| Sub-5 ms start-up time | Enables rapid system boot in telecom line cards and reconfigurable optical modules requiring fast clock availability. |
| Small DLF package (2.5 mm × 2.0 mm) | Supports high-density placement near SERDES transceivers - critical for QSFP-DD/OSFP module thermal and signal integrity. |
Applications
| 100G/400G Optical Transport | PCIe Gen 7 Reference Clocking |
|---|---|
|
Use Scenario: Provides primary reference clock for coherent DSPs and FEC engines in CFP2/OSFP pluggable optics. IC Role / Device Role / Timing Role: Fixed-frequency LVDS oscillator generating 156.25 MHz for OTU4/OTUCn framing and SerDes lane alignment. Use Value: ±25 ppm stability ensures long-term bit error rate compliance under thermal cycling; 100 fs jitter maintains BER <1e–15 in DP-QPSK modulation. |
Use Scenario: Supplies common clock to CPU, GPU, and NVMe controllers in AI accelerator servers. IC Role / Device Role / Timing Role: Low-jitter LVDS source meeting PCIe Gen 7 Common Clock jitter limit of 67 fs (peak-to-peak). Use Value: Integrated LDO rejects switching noise from VRMs; DLF package allows placement within 5 mm of root complex die. |
| High-Speed Switch Line Cards | 56G/112G PAM4 PHY Timing |
|
Use Scenario: Clocks multi-lane SerDes in 32-port 100GbE switches with distributed clock tree architecture. IC Role / Device Role / Timing Role: Primary timing source for gearbox ICs and retimers operating at 106.25 Gbps aggregate bandwidth. Use Value: Pin 1 standby enables per-slot power management; 2.5 mm × 2.0 mm footprint fits between ASIC and connector rows. |
Use Scenario: Synchronizes ADC/DAC sampling and DSP processing in 112G PAM4 transceivers for AI cluster interconnects. IC Role / Device Role / Timing Role: Ultra-low-phase-noise oscillator providing 156.25 MHz baseband clock for symbol timing recovery. Use Value: –156.5 dBc/Hz phase noise at 10 MHz offset suppresses reciprocal mixing in wideband RF front ends. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar oscillator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMK6D0I15625ADLFT | Same LMK6D family, identical 156.25 MHz LVDS output and DLF package, but uses Pin 2 for Standby (active low) instead of Pin 1. | Requires PCB layout change to route standby control to Pin 2; otherwise drop-in compatible in function and timing. | Select when existing design already routes standby to Pin 2 or when consolidating inventory across multiple LMK6D variants. |
| Si510-156.25M-AG | CMOS-output oscillator (not LVDS); 1.8V–3.3V supply; ±20 ppm stability; 1.3 ps RMS jitter (12 kHz–20 MHz) - higher than LMK6DA15625ADLFT's 100 fs. | Suitable only where single-ended drive suffices and jitter margin permits; not compliant with PCIe Gen 7 or 400G OTN specs. | Choose only for cost-sensitive, non-critical timing paths where LVDS differential signaling is unnecessary. |
Compared with LMK6DA15625ADLFT, LMK6D0I15625ADLFT offers identical performance with alternate pin mapping, while Si510-156.25M-AG trades 13× higher jitter and single-ended output for broader voltage flexibility and lower unit cost - making it unsuitable for next-gen SERDES but viable for legacy backplane clocks.
Availability
LMK6DA15625ADLFT is available at Aetrix Electronics and suitable for 100G/400G optical transport, PCIe Gen 7 server platforms, and high-speed switch line cards requiring stable component supply, long-term lifecycle support, and guaranteed traceable sourcing.
Supply support for LMK6DA15625ADLFT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and high-performance timing solutions, with manufacturing and test facilities across North America, Asia, and Europe.
The LMK6x product line was designed specifically for ultra-low-jitter, crystal-free clock generation in high-speed data communications - targeting 56G/112G PAM4, optical networking, and PCIe Gen 5–7 infrastructure where phase noise and aging stability are critical.
FAQ
What is the output type and load requirement for LMK6DA15625ADLFT?
The LMK6DA15625ADLFT provides LVDS differential output with 250–450 mV peak-to-peak swing into a 100 Ω differential load. It requires AC coupling via 0.1 µF capacitors on both OUTP and OUTN lines, and proper 100 Ω termination at the receiver end to maintain signal integrity and minimize reflections. DC-coupled operation is not supported.
Does LMK6DA15625ADLFT support multiple supply voltages?
Yes, LMK6DA15625ADLFT operates across 2.5V ±5% and 3.3V ±5% supply ranges, as specified in its "A" voltage/temperature rating. It does not support 1.8V operation - that variant uses suffix "B" (e.g., LMK6DBxxx). The internal LDO maintains regulation and PSRR performance across this dual-voltage range without external adjustment.
How is standby mode activated on LMK6DA15625ADLFT?
Standby mode on LMK6DA15625ADLFT is activated by pulling Pin 1 (ST) low to GND. This reduces supply current to ≤13 mA while holding internal state. The device resumes full operation within <5 ms after Pin 1 returns high. Pin 2 is NC and must remain unconnected - no pull-up or pull-down is required.
What is the jitter performance of LMK6DA15625ADLFT at 156.25 MHz?
At 156.25 MHz, LMK6DA15625ADLFT delivers 100 fs typical / 125 fs maximum RMS jitter (12 kHz–20 MHz integration bandwidth), –156.5 dBc/Hz phase noise at 10 MHz offset, and 13 ps peak-to-peak period jitter. These values meet and exceed PCIe Gen 7 common-clock (67 fs) and SRNS jitter requirements.
Is LMK6DA15625ADLFT pin-compatible with other LMK6D variants?
LMK6DA15625ADLFT shares the same DLF-6 package and pinout with all LMK6D variants (e.g., LMK6D0I15625ADLFT), including identical VDD, GND, OUTP, and OUTN locations. Only the standby/enable pin assignment differs: LMK6DA15625ADLFT uses Pin 1 (ST), while LMK6D0I15625ADLFT uses Pin 2. No other pin functions vary.
LMK6DA15625ADLFT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- LMK6x
- Package/Case:
- 6-VDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Base Resonator:
- Crystal
- Type:
- -
- Frequency:
- 156.25 MHz
- Function:
- Standby (Power Down)
- Output:
- LVDS
- Voltage - Supply:
- 2.5V ~ 3.3V
- Frequency Stability:
- ±25ppm
- Absolute Pull Range (APR):
- -
- Operating Temperature:
- -40°C ~ 85°C
- Spread Spectrum Bandwidth:
- -
- Current - Supply (Max):
- 75mA
- Ratings:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-VSON (2.5x2)
- Size / Dimension:
- 0.098" L x 0.079" W (2.50mm x 2.00mm)
- Height - Seated (Max):
- 0.039" (1.00mm)
LMK6DA15625ADLFT FAQ
1.How can I place an order for LMK6DA15625ADLFT through Aetrix?
Please submit a Request for Quotation (RFQ) for LMK6DA15625ADLFT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMK6DA15625ADLFT reliable?
The price and inventory of LMK6DA15625ADLFT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMK6DA15625ADLFT is usually 5 days.
3.What payment methods are accepted for LMK6DA15625ADLFT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMK6DA15625ADLFT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LMK6DA15625ADLFT?
LMK6DA15625ADLFT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMK6DA15625ADLFT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMK6DA15625ADLFT?
For technical support, including LMK6DA15625ADLFT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMK6DA15625ADLFT requirements.
6.How does Aetrix verify that LMK6DA15625ADLFT is sourced from the original manufacturer or authorized distributors?
All LMK6DA15625ADLFT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMK6DA15625ADLFT meets industry standards.
7.What is the process for return or replacement of LMK6DA15625ADLFT?
All LMK6DA15625ADLFT units undergo pre-shipment inspection (PSI). If there is an issue with LMK6DA15625ADLFT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMK6DA15625ADLFT part is unused and in its original packaging.
Return procedure for LMK6DA15625ADLFT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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