Texas Instruments LMK6PA15625ADLET
- Part No.:
- LMK6PA15625ADLET
- Manufacturer:
- Texas Instruments
- Category:
- Oscillators
- Package:
- 6-VDFN
- Datasheet:
-
LMK6PA15625ADLET.pdf
- Description:
- SILIC OSC XO 156.2500MHZ LVPECL
- Quantity:
- Payment:

- Shipping:

Inventory:5,344
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Product details
Overview
LMK6PA15625ADLET from Texas Instruments is a factory-programmed, ultra-low-jitter BAW-based fixed-frequency oscillator delivering 156.25 MHz LVPECL output with 100 fs typical RMS jitter (12 kHz–20 MHz), ±25 ppm total frequency stability over –40°C to 85°C, and integrated LDO for –72 dBc PSRR at 500 kHz. It serves as a high-precision reference clock in 100G/400G optical transport and PCIe Gen 7-compliant SERDES systems.
For engineers reviewing the LMK6PA15625ADLET datasheet, LMK6PA15625ADLET pinout, LMK6PA15625ADLET application, or LMK6PA15625ADLET equivalent, key selection criteria include differential LVPECL drive capability, sub-125 fs jitter compliance at 156.25 MHz, DLE-6 package compatibility, standby control via Pin 1 (active low), and supply noise immunity across 2.5V–3.3V operation.
Technical Context
The LMK6PA15625ADLET implements TI's Bulk-Acoustic Wave (BAW) resonator monolithically integrated with a fractional output divider and LVPECL output driver. Its architecture eliminates external crystal components while maintaining mechanical robustness and phase-noise performance of –158 dBc/Hz at 10 MHz offset.
It operates exclusively in fixed-frequency mode with factory-trimmed parameters: 156.25 MHz output, LVPECL interface, Standby (ST) function assigned to Pin 1 (active low), and voltage/temperature grade A (2.5V–3.3V ±5%, –40°C to 85°C). No user programming or configuration is supported.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Frequency | 156.25 MHz - precisely matched to Ethernet, OTN, and PCIe reference clock requirements. |
| RMS Jitter (12 kHz–20 MHz) | 100 fs typical / 125 fs max - meets PCIe Gen 7 common-clock jitter limit (67 fs) with margin. |
| Frequency Stability | ±25 ppm total - includes 10-year aging, temperature, voltage, and solder shift effects. |
| Supply Voltage Range | 2.5V–3.3V ±5% - supports dual-rail industrial and telecom power domains. |
| Operating Temperature | –40°C to +85°C - qualified for extended industrial environments including baseband units and line cards. |
| PSRR @ 500 kHz | –72 dBc - enables clean clocking without additional supply filtering in noisy PCB layouts. |
| Start-up Time | <5 ms - ensures rapid system initialization in hot-plug and recovery scenarios. |
Pinout & Package
VSON (DLE-6) package: 3.2 mm × 2.5 mm, 0.5 mm pitch, 6-pin exposed pad design optimized for thermal dissipation and board space efficiency in high-density optical and networking modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Standby (ST) | Active-low enable control; pulls output to high-impedance state when grounded, draws ≤13 mA in standby. |
| 2 | No Connect (NC) | Internally unconnected; must be left floating or tied to GND per layout guidelines. |
| 3 | GND | Signal and power ground reference; requires low-inductance connection to PCB ground plane. |
| 4 | OUTP | LVPECL positive differential output; 525–765 mV swing (AC-coupled, 3.3 V supply). |
| 5 | OUTN | LVPECL negative differential output; complements OUTP with 45–55% duty cycle and <200 ps rise/fall time. |
| 6 | VDD | Core power supply input; accepts 2.5V or 3.3V ±5%; integrates LDO for supply ripple rejection. |
Key Features
| Feature | Design Value |
|---|---|
| BAW Resonator Integration | Monolithic silicon-based micro-resonator replaces external crystals, eliminating aging drift and board-level tuning. |
| Differential LVPECL Output | 645 mV typical swing, 1.6 V common-mode voltage (3.3 V supply), enabling direct interface to SerDes CDR circuits. |
| Integrated LDO Regulation | –72 dBc PSRR at 500 kHz ripple suppresses switching noise from shared DC/DC converters without external ferrites. |
| Factory-Programmed Configuration | No external configuration required; all settings (frequency, output type, ST pin assignment, voltage grade) are laser-trimmed during manufacturing. |
| Small-Die VSON Package | DLE-6 footprint (3.2 × 2.5 mm) supports high-density placement adjacent to ASIC/FPGA clock inputs with minimal stub length. |
Applications
| 100G/400G Optical Transport | PCIe Gen 7 Reference Clocking |
|---|---|
Use Scenario: Provides primary reference clock for coherent DSPs and modulator drivers in DWDM line cards and pluggable optics (QSFP-DD, OSFP). IC Role / Device Role / Timing Role: Low-jitter master clock source synchronizing ADC/DAC sampling, FEC processing, and lane deskew logic. Use Value: 100 fs RMS jitter ensures BER <1e–15 under PAM4 modulation with 56G/112G baud rates. | Use Scenario: Supplies common-clock reference to CPU, GPU, and accelerator root complexes in AI/ML servers and storage controllers. IC Role / Device Role / Timing Role: PCIe Gen 7-compliant timing source meeting 67 fs common-clock jitter limit at 156.25 MHz. Use Value: Eliminates need for discrete crystal + buffer chain, reducing BOM count and layout complexity. |
| 5G Baseband Unit (BBU) | High-Speed Switch Fabric Clocking |
Use Scenario: Generates synchronized clocks for massive MIMO RFICs, fronthaul interfaces (eCPRI), and FPGA-based PHY processing in macro cell sites. IC Role / Device Role / Timing Role: Temperature-stable, low-phase-noise reference for multi-channel TDD synchronization and numerically controlled oscillators. Use Value: ±25 ppm stability over –40°C to 85°C avoids recalibration during outdoor thermal cycling. | Use Scenario: Drives clock inputs of multi-terabit switch ASICs (e.g., Broadcom Tomahawk, Marvell Teralynx) in data center top-of-rack and spine switches. IC Role / Device Role / Timing Role: Ultra-low-jitter core clock feeding PLLs that generate internal high-speed serdes lanes (56G+ PAM4). Use Value: Sub-125 fs jitter prevents deterministic jitter accumulation across cascaded clock trees. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar fixed-frequency oscillator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMK6P0A15625ADLET | Same LMK6P family, identical 156.25 MHz LVPECL output, but uses DLF-6 (2.5 mm × 2.0 mm) package instead of DLE-6. | Smaller footprint suits ultra-dense routing; slightly higher thermal resistance (107.9°C/W vs. 101.2°C/W). | Select when board area is constrained and thermal margin permits. |
| Si5341-A02781-GM | Programmable clock generator (not fixed-frequency); requires I²C configuration; 90 fs RMS jitter at 156.25 MHz. | Supports multiple output frequencies and formats (LVPECL/LVDS/HCSL); adds flexibility at cost of firmware dependency. | Select only if multi-frequency or multi-format support is required; not drop-in compatible. |
Compared with LMK6PA15625ADLET, the LMK6P0A15625ADLET offers identical electrical performance in a smaller package but reduced thermal headroom, while the Si5341-A02781-GM provides programmability at the expense of increased design complexity and non-drop-in replacement requirements.
Availability
LMK6PA15625ADLET is available at Aetrix Electronics and suitable for 100G optical modules, PCIe Gen 7 server platforms, and 5G baseband units requiring stable component supply, guaranteed long-term availability, and traceable sourcing.
Supply support for LMK6PA15625ADLET includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and clock solutions, with vertically integrated BAW fabrication and test capabilities.
The LMK6P product line delivers factory-programmed, ultra-low-jitter oscillators targeting high-speed serial link reference clocking in telecom, data center, and industrial infrastructure where crystal replacement and jitter margin are critical.
FAQ
What is the output type and drive strength of the LMK6PA15625ADLET?
The LMK6PA15625ADLET provides LVPECL output with 645 mV typical differential voltage swing (VOD) under AC-coupled 3.3 V supply conditions. Its output driver is designed for 50 Ω differential termination and delivers <200 ps rise/fall times, supporting direct interface to SerDes receivers without external level-shifting or buffering.
Does the LMK6PA15625ADLET require external configuration or programming?
No, the LMK6PA15625ADLET is factory-programmed with fixed parameters: 156.25 MHz frequency, LVPECL output, Standby (ST) function on Pin 1 (active low), and voltage/temperature grade A. It operates immediately upon power-up with no I²C, SPI, or pin-strapping configuration required.
What is the total frequency stability specification for the LMK6PA15625ADLET over its lifetime?
The LMK6PA15625ADLET guarantees ±25 ppm total frequency stability over its full operational life, inclusive of initial tolerance, variation across –40°C to +85°C, supply voltage changes (2.5V–3.3V ±5%), and 10-year aging at 25°C - verified per TI's production test flow.
How does the LMK6PA15625ADLET achieve immunity to power supply noise?
The LMK6PA15625ADLET integrates an on-chip LDO regulator that delivers –72 dBc PSRR at 500 kHz ripple. This allows it to maintain ultra-low jitter even when powered from noisy DC/DC converters, eliminating the need for external LC filters or ferrite beads in most high-speed board designs.
Is the LMK6PA15625ADLET pin-compatible with other LMK6P variants?
Yes, all LMK6P devices in the DLE-6 package share identical 6-pin VSON footprints and pinout (Pin 1 = ST/OE, Pin 4 = OUTP, Pin 5 = OUTN, Pin 6 = VDD). However, functional differences (e.g., OE vs. ST assignment, voltage grade) mean electrical compatibility must be verified per datasheet before substitution.
LMK6PA15625ADLET Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- LMK6x
- Package/Case:
- 6-VDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Base Resonator:
- Silicon
- Type:
- XO (Standard)
- Frequency:
- 156.25 MHz
- Function:
- Standby (Power Down)
- Output:
- LVPECL
- Voltage - Supply:
- 2.5V ~ 3.3V
- Frequency Stability:
- ±25ppm
- Absolute Pull Range (APR):
- -
- Operating Temperature:
- -40°C ~ 85°C
- Spread Spectrum Bandwidth:
- -
- Current - Supply (Max):
- 87mA
- Ratings:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-VSON (3.2x2.5)
- Size / Dimension:
- 0.126" L x 0.098" W (3.20mm x 2.50mm)
- Height - Seated (Max):
- 0.039" (1.00mm)
LMK6PA15625ADLET FAQ
1.How can I place an order for LMK6PA15625ADLET through Aetrix?
Please submit a Request for Quotation (RFQ) for LMK6PA15625ADLET on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMK6PA15625ADLET reliable?
The price and inventory of LMK6PA15625ADLET are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMK6PA15625ADLET is usually 5 days.
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Once your LMK6PA15625ADLET order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMK6PA15625ADLET?
For technical support, including LMK6PA15625ADLET datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMK6PA15625ADLET requirements.
6.How does Aetrix verify that LMK6PA15625ADLET is sourced from the original manufacturer or authorized distributors?
All LMK6PA15625ADLET products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMK6PA15625ADLET meets industry standards.
7.What is the process for return or replacement of LMK6PA15625ADLET?
All LMK6PA15625ADLET units undergo pre-shipment inspection (PSI). If there is an issue with LMK6PA15625ADLET, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMK6PA15625ADLET part is unused and in its original packaging.
Return procedure for LMK6PA15625ADLET:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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