Texas Instruments LMKDB1104Z100REXR

Overview

LMKDB1104Z100REXR from Texas Instruments is a 2-input, 4-output LP-HCSL PCIe clock multiplexer supporting Gen 1 to Gen 7, DB2000QL-compliant, with 100Ω output impedance, 3.3V/1.8V dual-supply operation, and –40°C to 105°C ambient range - deployed in server motherboard clock trees for PCIe root complex and endpoint timing distribution.

For engineers reviewing the LMKDB1104Z100REXR datasheet, LMKDB1104Z100REXR pinout, LMKDB1104Z100REXR application, or LMKDB1104Z100REXR equivalent, this page delivers verified electrical specs, validated pin functions, PCIe Gen 7–compliant jitter performance (2.1fs RMS), fail-safe input behavior, and real-world implementation context for high-speed serial interface timing integrity.

Technical Context

The LMKDB1104Z100REXR implements a dual-differential-input, quad-differential-output LP-HCSL clock mux architecture with programmable 100Ω output impedance and 3-level clock select logic (CLKIN0/CLKIN1 routing per bank). It supports both Common Clock (CC) and Independent Reference (IR) PCIe topologies and accepts input clocks with or without spread-spectrum modulation (SSC).

It integrates loss-of-signal (LOS#) detection, automatic output disable on input failure, individual output enable (OE#) control, and Side-Band Interface (SBI) for high-speed output toggling - all while maintaining <2.1fs RMS additive jitter at PCIe Gen 7 frequencies (32GHz reference bandwidth) and meeting DB2000QL AC/DC test load requirements.

Key Specifications

Pinout & Package

LMKDB1104Z100REXR is housed in a 4mm × 4mm REX (VQFN-28) package with exposed thermal pad (GND). Pin count and layout match the LMKDB1204 family variant; pin functions are validated per TI SNAS927A Rev. APRIL 2026.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar PCIe clock mux applications.

Compared with LMKDB1104Z100REXR, LMKDB1204REXR adds runtime impedance and interface mode flexibility at identical footprint and thermal profile, while LMKDB1104Z85REXR trades configurability for lower BOM cost in static 85Ω designs.

Availability

LMKDB1104Z100REXR is available at Aetrix Electronics and suitable for server motherboard design, NIC/SmartNIC production, and hardware accelerator timing applications requiring stable component supply, long-term lifecycle assurance, and DB2000QL-compliant PCIe Gen 7 clock integrity.

Supply support for LMKDB1104Z100REXR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and clock solutions, with decades of PCIe timing expertise and broad industry qualification.

The LMKDB family is designed specifically for ultra-low-jitter PCIe clock distribution in next-generation data center infrastructure - targeting Gen 5 through Gen 7 compliance with DB2000QL, fail-safe operation, and flexible power architecture.

FAQ

What is the output impedance configuration of LMKDB1104Z100REXR?

The LMKDB1104Z100REXR is factory-configured for fixed 100Ω differential LP-HCSL output impedance, selected via internal bonding option - confirmed by the "Z100" suffix and validated in TI SNAS927A Section 4 Device Comparison. This eliminates need for external termination in PCIe Gen 5+ designs and matches AC-coupled channel requirements without requiring vZOUT_SEL pin control. The LMKDB1104Z100REXR does not support runtime impedance switching.

Does LMKDB1104Z100REXR support PCIe Gen 7 timing requirements?

Yes, the LMKDB1104Z100REXR delivers 2.1fs maximum RMS additive jitter (12kHz–20MHz) at PCIe Gen 7 frequencies, as specified in TI SNAS927A Section 1 Features and Table 6-5 Electrical Characteristics. This value satisfies the most stringent Gen 7 jitter budget for 32 GT/s NRZ links and is measured under DB2000QL-compliant test conditions with 100Ω load and 156.25MHz/312.5MHz reference clocks.

How does the fail-safe input feature operate on LMKDB1104Z100REXR?

The LMKDB1104Z100REXR implements fail-safe biasing on both CLKIN0 and CLKIN1 differential pairs - internal resistive networks hold inputs at valid logic thresholds even when unconnected or unterminated. This prevents metastability and undefined state propagation during hot-plug, cable disconnect, or reference source failure. The behavior is inherent to the input circuitry and requires no external components or configuration.

Can LMKDB1104Z100REXR be used in Independent Reference (IR) PCIe architectures?

Yes, the LMKDB1104Z100REXR supports IR mode via its 3-level ^vCLKIN_SEL_tri pin: mid-level selection routes CLKIN0 to Bank 0 (CLK0/CLK1) and CLKIN1 to Bank 1 (CLK2/CLK3), enabling separate reference domains per PCIe hierarchy. This functionality is explicitly documented in TI SNAS927A Table 5-2 Pin Functions and Section 8.3 Feature Description, and is electrically validated for simultaneous Gen 7 operation on both banks.

What is the thermal performance of LMKDB1104Z100REXR in its REX package?

The LMKDB1104Z100REXR in the 4mm × 4mm REX (VQFN-28) package has a junction-to-ambient thermal resistance (RθJA) of 44.2°C/W, as specified in TI SNAS927A Section 6.4 Thermal Information. At full 3.3V operation and 105°C ambient, this enables reliable continuous operation with standard PCB copper pour and no forced airflow - validated for server motherboard and SmartNIC thermal envelopes per JEDEC JESD51-2.