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Texas Instruments LMKDB1104Z85REXR
- Part No.:
- LMKDB1104Z85REXR
- Manufacturer:
- Texas Instruments
- Category:
- Application Specific Clock/Timing
- Package:
- 28-VFQFN Exposed Pad
- Datasheet:
-
LMKDB1104Z85REXR.pdf
- Description:
- 4-output LP-HCSL clock buffer
- Quantity:
- Payment:
- Shipping:
Inventory:1,874
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Product details
Overview
LMKDB1104Z85REXR from Texas Instruments is a 2-input, 4-output LP-HCSL PCIe clock multiplexer supporting Gen 1 to Gen 7, DB2000QL-compliant, with 85Ω output impedance, 31fs max 12kHz–20MHz RMS additive jitter at 156.25MHz, and –40°C to 105°C operation. It serves as a fail-safe, low-jitter clock routing solution in high-speed server and accelerator interconnects.
For engineers reviewing the LMKDB1104Z85REXR datasheet, LMKDB1104Z85REXR pinout, LMKDB1104Z85REXR application, or LMKDB1104Z85REXR equivalent, key selection criteria include PCIe Gen 7 additive jitter (2.1fs), dual-input fail-safe LOS detection, individual output enable control, and VQFN-28 (4mm × 4mm) package compatibility with 1.8V/3.3V supplies.
Technical Context
The LMKDB1104Z85REXR implements a differential 2:4 clock mux architecture with programmable input selection (CLKIN0/CLKIN1 per bank or globally), automatic output disable on loss-of-signal, and side-band interface (SBI) or SMBus control options. Its LP-HCSL outputs meet DB2000QL AC/DC timing, slew rate, and crossing-point specifications across PCIe Gen 1–7 frequencies.
It supports flexible power sequencing via PWRGD/PWRDN# pin, configurable 85Ω/100Ω output impedance via vZOUT_SEL, and independent OE# control for each of its four differential outputs. The device operates with separate analog (VDDA), digital (VDD_DIG), input (VDD_IN0/VDD_IN1), and output-bank (VDDO_BANK0/BANK1) supplies to isolate noise paths.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Additive Jitter (12kHz–20MHz) | 31fs max at 156.25MHz - meets PCIe Gen 7 ultra-low jitter requirement for clean clock distribution |
| PCIe Gen Support | Gen 1 through Gen 7 - full backward/forward compatibility with evolving PCIe signaling standards |
| Output Count & Type | 4 LP-HCSL differential outputs - enables fanout to four PCIe PHYs or endpoints without external buffers |
| Output Impedance | 85Ω (factory-configured) - matches standard LP-HCSL trace impedance for minimal reflection |
| Operating Temp Range | –40°C to +105°C ambient - qualified for server motherboard and NIC thermal environments |
| Supply Voltages | 1.8V ±10% and 3.3V ±10% - dual-voltage support simplifies integration into mixed-supply systems |
| Input Architecture | 2 differential clock inputs with fail-safe LOS detection - ensures robust switching during reference failure |
Pinout & Package
LMKDB1104Z85REXR uses a 28-pin REX (VQFN) package measuring 4mm × 4mm with exposed thermal pad (GND). Pin functions are validated per TI SNAS927A datasheet Section 5.2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| CLKIN0_P / CLKIN0_N | Differential clock input 0 | Primary reference source; supports SSC and CC/IR PCIe topologies |
| CLKIN1_P / CLKIN1_N | Differential clock input 1 | Redundant or secondary reference; selectable per bank via ^vCLKIN_SEL_tri |
| CLK0_P / CLK0_N to CLK3_P / CLK3_N | LP-HCSL differential outputs | Four independent, impedance-matched outputs; each controlled by dedicated OE# pin |
| ^OE0# to ^OE3# | Active-low output enable | Individual hardware control for each output; internal pullup eliminates need for external resistors |
| vZOUT_SEL | Output impedance select | Pulldown-default = 85Ω; driven high = 100Ω - configures termination to match PCB stackup |
| LOS# | Loss-of-signal indicator | Open-drain active-low flag; asserts within 120ns of input failure - enables system-level fault response |
| ^PWRGD/PWRDN# | Power good / power-down control | First rising edge enables startup; subsequent toggles enter/exit low-power mode - supports dynamic power management |
| VDDO_BANK0 / VDDO_BANK1 | Output bank power supplies | Independent 1.8V/3.3V rails per bank allow mixed-voltage endpoint interfacing |
Key Features
| Feature | Design Value |
|---|---|
| DB2000QL compliance | Fully satisfies all AC/DC electrical, timing, and jitter requirements for PCIe clock ICs - eliminates pre-compliance validation effort |
| Ultra-low Gen 7 jitter | 2.1fs max additive jitter - enables margin-critical Gen 7 link training and BER <10⁻¹² at 64 GT/s |
| Fail-safe input architecture | LOS# detection + automatic output disable on input loss - prevents downstream clock domain instability |
| Flexible control interface | SMBus or SBI option (via vSMB_EN) - allows either register-based configuration or high-speed pin-strapped enable/disable |
| Programmable output impedance | 85Ω or 100Ω selection via vZOUT_SEL - adapts to varying PCB trace impedances without redesign |
| Independent output banks | VDDO_BANK0/BANK1 separation - isolates noise between output groups driving different PCIe slots or devices |
Applications
| Server Motherboard Clock Distribution | NIC/SmartNIC PCIe Timing |
|---|---|
|
Use Scenario: Distributing low-jitter reference clocks from a single oscillator to multiple PCIe slots, CPU interconnects, and platform controllers on a 2U/4U server board. IC Role / Device Role / Timing Role: 2-input, 4-output PCIe clock mux providing Gen 7–compliant LP-HCSL signals with bank-selectable inputs and fail-safe LOS monitoring. Use Value: Eliminates need for discrete buffer chains while maintaining <2.1fs jitter - improves signal integrity margin and reduces BOM count by 3+ components per slot. |
Use Scenario: Delivering synchronized, low-additive-jitter clocks to dual-port 100G SmartNICs with independent PCIe Gen 5 x16 lanes and on-board accelerators. IC Role / Device Role / Timing Role: Clock routing hub enabling independent clock enable/disable per port and seamless switchover between primary and backup references. Use Value: Enables hot-failover clocking with <120ns LOS response and <70ns automatic output disable - maintains NIC link stability during reference loss. |
| Hardware Accelerator Timing | HPC Interconnect Clocking |
|
Use Scenario: Providing phase-aligned, ultra-low-jitter clocks to FPGA-based AI accelerators with multiple PCIe Gen 6 x8 interfaces and CXL memory controllers. IC Role / Device Role / Timing Role: Precision clock mux supporting independent output enable and impedance tuning to match heterogeneous load capacitance across FPGA I/O banks. Use Value: Achieves 31fs total additive jitter at 156.25MHz - meets strict setup/hold margins for 64 GT/s CXL 3.0 SerDes PHYs. |
Use Scenario: Synchronizing clock domains across GPU compute nodes interconnected via NVLink or PCIe Gen 7 switches in AI training clusters. IC Role / Device Role / Timing Role: Low-phase-noise clock distributor with dual-input redundancy and bank-isolated power domains to suppress cross-talk between high-current GPU clock trees. Use Value: Delivers <5fs Gen 5 and <2.1fs Gen 7 jitter - reduces inter-node timing skew below 100fs, critical for deterministic RDMA latency. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar PCIe clock mux applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LMKDB1204RTER | 4-output, 2-input mux with selectable 85Ω/100Ω output impedance (vZOUT_SEL); same REX package and pinout | Supports identical PCIe Gen 1–7 and DB2000QL compliance; differs only in factory-set impedance (Z85 vs Z100) | Select LMKDB1204RTER if 100Ω output termination is required for specific PCB stackup or legacy layout reuse |
| LMKDB1104FS85REXR | Same 1×4 buffer topology and 85Ω output; adds fail-safe outputs (not just inputs) and enhanced ESD protection | Targeted at safety-critical or high-reliability deployments where output short-circuit immunity is mandated | Choose LMKDB1104FS85REXR when system-level fault containment requires output-side fail-safe behavior beyond input monitoring |
Compared with LMKDB1104Z85REXR, LMKDB1204RTER offers field-selectable impedance but identical jitter and feature set, while LMKDB1104FS85REXR trades configurability for hardened output protection-making the Z85 variant optimal for cost-sensitive, high-volume Gen 7 server clocking where input fail-safety suffices.
Availability
LMKDB1104Z85REXR is available at Aetrix Electronics and suitable for server motherboard design, NIC/SmartNIC development, and hardware accelerator timing applications requiring stable component supply, long-term lifecycle assurance, and DB2000QL-compliant performance.
Supply support for LMKDB1104Z85REXR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and clock solutions, with decades of expertise in high-performance timing ICs for datacenter and communications infrastructure.
The LMKDB family was designed specifically for PCIe Gen 1–7 clock distribution in servers, accelerators, and networking equipment-emphasizing ultra-low jitter, DB2000QL compliance, and robust fail-safe operation under thermal and supply stress.
FAQ
What PCIe generations does the LMKDB1104Z85REXR support?
The LMKDB1104Z85REXR supports PCIe Gen 1 through Gen 7, verified by TI's DB2000QL compliance testing and jitter characterization - including 2.1fs maximum additive jitter at Gen 7 (64 GT/s) and 5fs at Gen 5 (32 GT/s). This ensures full interoperability across legacy and next-generation PCIe platforms without firmware or layout changes.
Does the LMKDB1104Z85REXR require external pull-up or pull-down resistors on control pins?
Most control pins on the LMKDB1104Z85REXR include integrated biasing: ^OE0#–^OE3# have internal pullups, vZOUT_SEL and vSMB_EN have internal pulldowns, and ^vCLKIN_SEL_tri has both. External resistors are only required on open-drain LOS# and SMBus pins (SMB_DATA/SMB_CLK), per TI SNAS927A Section 5.2.
How is output impedance configured on the LMKDB1104Z85REXR?
The LMKDB1104Z85REXR is factory-configured for 85Ω output impedance (Z85 suffix). The vZOUT_SEL pin allows runtime reconfiguration: logic low = 85Ω, logic high = 100Ω. This matches standard LP-HCSL trace impedances and is validated per DB2000QL AC test loads in TI's electrical characteristics table.
What is the function of the ^PWRGD/PWRDN# pin on the LMKDB1104Z85REXR?
The ^PWRGD/PWRDN# pin on the LMKDB1104Z85REXR serves dual roles: the first rising edge after power-up acts as Power Good to initiate device startup; subsequent low-to-high transitions trigger power-down mode. In power-down, outputs disable and current drops to <100µA - enabling dynamic power gating in PCIe link idle states.
Is the LMKDB1104Z85REXR pin-compatible with other LMKDB12xx devices?
No - the LMKDB1104Z85REXR is a 1-input, 4-output buffer (per Table 4-1), whereas LMKDB12xx parts like LMKDB1204 are 2-input, 4-output muxes. Though both use the REX-28 package, their pin functions differ significantly (e.g., CLKIN1 pins exist only on LMKDB12xx), making them functionally and pinout-incompatible replacements.
LMKDB1104Z85REXR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- LMKDB1xxx
- Package/Case:
- 28-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- PLL:
- No
- Main Purpose:
- PCI Express (PCIe)
- Input:
- Clock
- Output:
- LP-HCSL
- Number of Circuits:
- 1
- Ratio - Input:Output:
- 1:4
- Differential - Input:Output:
- Yes/Yes
- Frequency - Max:
- 400MHz
- Voltage - Supply:
- 1.71V ~ 1.89V, 2.97V ~ 3.6V
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Mounting Type:
- Surface Mount
- Grade:
- -
- Qualification:
- -
- Supplier Device Package:
- 28-VQFN (4x4)
LMKDB1104Z85REXR FAQ
1.How can I place an order for LMKDB1104Z85REXR through Aetrix?
Please submit a Request for Quotation (RFQ) for LMKDB1104Z85REXR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMKDB1104Z85REXR reliable?
The price and inventory of LMKDB1104Z85REXR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMKDB1104Z85REXR is usually 5 days.
3.What payment methods are accepted for LMKDB1104Z85REXR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMKDB1104Z85REXR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LMKDB1104Z85REXR?
LMKDB1104Z85REXR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMKDB1104Z85REXR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMKDB1104Z85REXR?
For technical support, including LMKDB1104Z85REXR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMKDB1104Z85REXR requirements.
6.How does Aetrix verify that LMKDB1104Z85REXR is sourced from the original manufacturer or authorized distributors?
All LMKDB1104Z85REXR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMKDB1104Z85REXR meets industry standards.
7.What is the process for return or replacement of LMKDB1104Z85REXR?
All LMKDB1104Z85REXR units undergo pre-shipment inspection (PSI). If there is an issue with LMKDB1104Z85REXR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMKDB1104Z85REXR part is unused and in its original packaging.
Return procedure for LMKDB1104Z85REXR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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