Texas Instruments LMP2014MT
- Part No.:
- LMP2014MT
- Manufacturer:
- Texas Instruments
- Category:
- Instrumentation, Op Amps, Buffer Amps
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LMP2014MT.pdf
- Description:
- IC OPAMP GP 4 CIRCUIT 14TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LMP2014MT from Texas Instruments is a quad high-precision, rail-to-rail output operational amplifier optimized for DC-critical applications requiring ultra-low offset voltage (60 µV max), zero 1/f noise (35 nV/√Hz flat), and exceptional long-term stability (0.006 µV/month drift). It operates from 2.7 V to 5.25 V and delivers 3 MHz gain-bandwidth with 4 V/µs slew rate - ideal for thermocouple amplification, strain-gauge bridge interfaces, and precision ADC input buffering in industrial instrumentation.
For engineers reviewing the LMP2014MT datasheet, LMP2014MT pinout, LMP2014MT application, or LMP2014MT equivalent, key selection considerations include its patented auto-zero architecture eliminating 1/f noise, copper leadframe minimizing thermocouple errors, no external capacitor requirement, and guaranteed rail-to-rail output swing within 30 mV of supply rails at 2 kΩ load.
Technical Context
The LMP2014MT employs a continuous-time auto-zeroing architecture that actively measures and corrects input offset voltage without chopping artifacts, enabling clean spectral performance with no mixing products near 30 kHz. Its input stage uses picoamp-level bias currents (±3 pA) and achieves 130 dB CMRR and 120 dB PSRR across 2.7–5.25 V supply range.
This architecture enables stable operation into capacitive loads up to 500 pF without external compensation, supports fast overload recovery (≤50 ms), and maintains <0.02% THD+N at 1 kHz with 2 VPP output - critical for high-fidelity signal conditioning before 12-bit+ ADCs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Offset Voltage | 60 µV max over temperature - ensures ≤5 LSB error in 12-bit ADC systems over 30-year life at 50°C |
| Input-Referred Voltage Noise | 35 nV/√Hz flat (no 1/f corner) - eliminates time-dependent measurement drift in DC-coupled sensors |
| Rail-to-Rail Output Swing | Within 30 mV of supply rails at 2 kΩ - maximizes dynamic range for single-supply 5 V ADCs |
| Gain-Bandwidth Product | 3 MHz - supports stable closed-loop gains up to 100 with ≥2.5 MHz usable bandwidth |
| Supply Current per Channel | 1.2 mA typical - enables low-power precision sensing in battery-operated instrumentation |
| Common-Mode Rejection Ratio | 130 dB - rejects >99.999% of common-mode interference in bridge sensor configurations |
| Power Supply Rejection Ratio | 120 dB - maintains accuracy despite ±100 mV ripple on 5 V rail |
Pinout & Package
Package: 14-pin TSSOP (PW), RoHS-compliant, moisture sensitivity level 1, rated for 0°C to 70°C operation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Inverting Input (Ch A) | Differential input node for first op-amp channel; accepts common-mode voltage from −0.3 V to VCC+0.3 V |
| 2 | Non-Inverting Input (Ch A) | Reference input for Ch A; matched impedance critical for CMRR optimization in instrumentation amps |
| 3 | Output (Ch A) | Rail-to-rail output capable of sourcing/sinking ≥12 mA; settles to 0.01% in 1.4 µs |
| 4 | V− (GND) | Analog ground reference; copper leadframe minimizes thermocouple EMF vs. PCB copper |
| 5 | Non-Inverting Input (Ch B) | Second channel positive input; identical DC/AC specs to Pin 2 |
| 6 | Inverting Input (Ch B) | Second channel negative input; supports matched resistor networks for dual-channel bridges |
| 7 | Output (Ch B) | Independent rail-to-rail output; no crosstalk >100 dB at 1 kHz |
| 8 | V+ | Positive supply rail (2.7–5.25 V); PSRR of 120 dB suppresses supply noise coupling |
| 9 | Output (Ch C) | Third channel output; shares same auto-zero calibration engine as Ch A/B for correlated drift cancellation |
| 10 | Inverting Input (Ch C) | Third channel negative input; supports multi-sensor synchronous sampling |
| 11 | Non-Inverting Input (Ch C) | Third channel positive input; enables 3-channel differential acquisition |
| 12 | Non-Inverting Input (Ch D) | Fourth channel positive input; allows full-bridge + reference channel configuration |
| 13 | Inverting Input (Ch D) | Fourth channel negative input; supports independent gain setting per channel |
| 14 | Output (Ch D) | Fourth rail-to-rail output; enables simultaneous buffering of four sensor channels |
Key Features
| Feature | Design Value |
|---|---|
| No 1/f noise architecture | Flat 35 nV/√Hz voltage noise down to 0.001 Hz - eliminates integration-time-dependent drift in precision weigh scales |
| Copper leadframe construction | Reduces thermocouple EMF to <0.0014°C-equivalent error - critical for sub-µV-level thermocouple amplification |
| Auto-zero offset correction | Continuous real-time calibration achieving 0.006 µV/month long-term drift - enables 30-year calibration-free operation |
| No external capacitors required | Eliminates dielectric absorption and leakage-induced settling delays - achieves full accuracy within 1.4 µs after power-up |
| Rail-to-rail output with 30 mV headroom | Delivers 4.92 VOUT at 5 V supply into 10 kΩ - preserves >98% of ADC full-scale range |
| Fast overload recovery | ≤50 ms recovery from 2× full-scale overdrive - prevents data loss during transient events in data acquisition systems |
Applications
| Precision Instrumentation Amplifier | Thermocouple Amplifier |
|---|---|
Use Scenario: High-gain (≥1000×) amplification of µV-level thermocouple outputs in industrial ovens and environmental chambers. IC Role / Device Role / Timing Role: Primary front-end amplifier providing cold-junction compensation interface and 12-bit ADC drive capability. Use Value: Copper leadframe eliminates thermocouple EMF errors; zero 1/f noise ensures stable µV-level readings over hours-long measurements. |
Use Scenario: Low-drift amplification of Type-K thermocouples (41 µV/°C) with cold-junction compensation in HVAC control units. IC Role / Device Role / Timing Role: Dual-channel configuration: one channel for thermocouple signal, second for RTD-based cold-junction sensing. Use Value: 60 µV max VOS and 0.015 µV/°C TCVOS limit temperature error to <0.1°C over 0–70°C operating range. |
| Strain Gauge Bridge Amplifier | ADC Input Buffer |
Use Scenario: 4-wire full-bridge strain gauge readout in load cells and pressure transducers with >100 dB CMRR requirement. IC Role / Device Role / Timing Role: Quad configuration enables independent amplification of bridge arms plus reference and excitation monitoring. Use Value: 130 dB CMRR rejects common-mode noise from shared excitation supplies; rail-to-rail output drives 5 V ADCs to full scale. |
Use Scenario: Driving SAR and sigma-delta ADC inputs in portable data loggers requiring 12-bit+ accuracy over battery life. IC Role / Device Role / Timing Role: Final gain stage before ADC, providing low-noise, low-distortion signal conditioning with fast settling. Use Value: 1.4 µs settling to 0.01% enables 100 kSPS sampling; no 1/f noise ensures consistent SNR regardless of integration time. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar precision operational amplifier applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| OPA2189IDR | Zero-drift architecture with 5.2 µV max VOS, 5.2 MHz GBW, but requires external 10 nF capacitor for stability | Better initial accuracy but higher supply current (1.3 mA/ch vs. 1.2 mA); less suitable for capacitor-free layouts | Select OPA2189IDR only when <5 µV VOS is mandatory and board space allows external capacitor placement |
| AD8629ARZ | Chopper-stabilized design with 1 µV max VOS, but exhibits 1/f noise corner at 10 Hz and 250 ms overload recovery | Superior DC offset spec but introduces mixing artifacts near 150 kHz; unsuitable for wideband sensor signals | Choose AD8629ARZ for pure DC applications where bandwidth <100 kHz and recovery time >200 ms are acceptable |
Compared with OPA2189IDR and AD8629ARZ, the LMP2014MT uniquely combines capacitor-free operation, zero 1/f noise, and 50 ms overload recovery - making it optimal for high-accuracy, wideband, low-maintenance sensor interfaces where layout simplicity and time-domain stability are critical.
Availability
LMP2014MT is available at Aetrix Electronics and suitable for precision instrumentation, industrial sensor conditioning, and high-reliability data acquisition systems requiring stable component supply across extended product lifecycles.
Supply support for LMP2014MT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with over 90 years of innovation in precision signal chain solutions.
The LMP2014MT belongs to TI's LMP™ precision amplifier family, engineered specifically for ultra-stable, low-drift, zero-1/f-noise operation in demanding DC-critical measurement systems.
FAQ
What is the maximum supply voltage rating for the LMP2014MT?
The LMP2014MT has an absolute maximum supply voltage of 5.8 V, but its specified operating range is 2.7 V to 5.25 V. Operation above 5.25 V may cause parametric degradation or reliability risk, and the device is not characterized beyond this limit. For robust 5 V system design, the LMP2014MT delivers full performance at 5.0 V nominal supply with 120 dB PSRR ensuring immunity to typical rail ripple.
Does the LMP2014MT require external compensation capacitors?
No, the LMP2014MT does not require external capacitors for stability - a key differentiator from many zero-drift amplifiers. Its internal compensation enables unity-gain stable operation into capacitive loads up to 500 pF without oscillation. This eliminates dielectric absorption errors and reduces PCB area, making the LMP2014MT ideal for high-accuracy, low-settling-time applications where external components would compromise performance.
How does the LMP2014MT achieve zero 1/f noise?
The LMP2014MT uses a patented continuous-time auto-zeroing architecture that eliminates 1/f noise by dynamically correcting input offset without clocked chopping. Unlike chopper-stabilized amplifiers, it avoids mixing products and distortion by operating in the analog domain with no sampling artifacts. This results in flat 35 nV/√Hz voltage noise from 0.001 Hz upward - verified in TI's SNOSAK6B datasheet Figure 6 and Application Note Section "THE BENEFITS OF LMP2014 NO 1/f NOISE".
What is the typical input bias current of the LMP2014MT?
The LMP2014MT exhibits input bias current of ±3 pA (min) and ±6 pA (max) across temperature, with typical values near ±3 pA at 25°C. These currents flow differentially - into one input and out the other - minimizing offset voltage shift in balanced configurations. At high temperatures (70°C) and low common-mode voltages, bias current rises to ~0.5 nA, so designers should avoid series input resistors in such conditions to prevent added offset error.
Can the LMP2014MT drive ADC inputs directly in single-supply 5 V systems?
Yes, the LMP2014MT is explicitly designed for direct ADC interfacing in 5 V single-supply systems. Its rail-to-rail output swings to within 30 mV of both rails (e.g., 4.92 V at VCC = 5 V into 10 kΩ), maximizing ADC dynamic range. Combined with 1.4 µs settling to 0.01%, 35 nV/√Hz noise, and no 1/f contribution, the LMP2014MT ensures 12-bit+ accuracy without additional buffering - as validated in TI's "LMP2014 AS ADC INPUT AMPLIFIER" application section.
LMP2014MT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- LMP®
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Amplifier Type:
- General Purpose
- Number of Circuits:
- 4
- Output Type:
- Rail-to-Rail
- Slew Rate:
- 3V/µs
- Gain Bandwidth Product:
- 3 MHz
- -3db Bandwidth:
- -
- Current - Input Bias:
- 0.3 pA
- Voltage - Input Offset:
- 0.12 µV
- Current - Supply:
- 930µA (x4 Channels)
- Current - Output / Channel:
- 17 mA
- Voltage - Supply Span (Min):
- 2.7 V
- Voltage - Supply Span (Max):
- 5.25 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
LMP2014MT FAQ
1.How can I place an order for LMP2014MT through Aetrix?
Please submit a Request for Quotation (RFQ) for LMP2014MT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LMP2014MT reliable?
The price and inventory of LMP2014MT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LMP2014MT is usually 5 days.
3.What payment methods are accepted for LMP2014MT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LMP2014MT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LMP2014MT?
LMP2014MT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LMP2014MT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LMP2014MT?
For technical support, including LMP2014MT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LMP2014MT requirements.
6.How does Aetrix verify that LMP2014MT is sourced from the original manufacturer or authorized distributors?
All LMP2014MT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LMP2014MT meets industry standards.
7.What is the process for return or replacement of LMP2014MT?
All LMP2014MT units undergo pre-shipment inspection (PSI). If there is an issue with LMP2014MT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LMP2014MT part is unused and in its original packaging.
Return procedure for LMP2014MT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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