My Inquiry
My Account
Texas Instruments LP2987AIMM-5.0/NOPB
- Part No.:
- LP2987AIMM-5.0/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Datasheet:
-
LP2987AIMM-5.0/NOPB.pdf
- Description:
- IC REG LINEAR 5V 200MA 8VSSOP
- Quantity:
- Payment:
- Shipping:
Inventory:993
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LP2987AIMM-5.0/NOPB from Texas Instruments is a fixed-output, 200 mA ultra-low-dropout linear voltage regulator with programmable power-on reset delay and 5.0 V output. It uses a vertically integrated PNP (VIP) process to achieve 180 mV dropout at 200 mA, <2 µA shutdown quiescent current, and ±0.5% output voltage accuracy (A-grade), targeting noise-sensitive portable power rails in cellular phones and camcorders.
For engineers reviewing the LP2987AIMM-5.0/NOPB datasheet, LP2987AIMM-5.0/NOPB pinout, LP2987AIMM-5.0/NOPB application, or LP2987AIMM-5.0/NOPB equivalent, key selection criteria include dropout performance at full load, reset delay configurability via external capacitor, ground pin current vs. load, thermal limits for VSSOP-8, and compatibility with low-ESR tantalum or ceramic output capacitors.
Technical Context
The LP2987AIMM-5.0/NOPB implements a precision bandgap reference and error amplifier driving a PNP pass transistor, enabling stable regulation down to 180 mV input–output differential. Its error flag (open-collector) asserts low when output drops >5% below nominal and doubles as a power-on reset signal when paired with an external capacitor on the DELAY pin.
Unlike the LP2988 variant, this part lacks a Bypass pin and associated low-noise enhancement circuitry-its output noise is 100 µVRMS (300 Hz–50 kHz). The VSSOP-8 package provides 200°C/W junction-to-ambient thermal resistance, requiring careful PCB copper area management above 100 mA continuous load.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 5.0 V ±0.5% (A-grade) at 25°C; ensures stable logic supply for microcontrollers and analog subsystems without external feedback. |
| Dropout Voltage | 180 mV @ 200 mA load (typical); enables operation from 5.18 V input while maintaining regulation-critical for single-cell Li-ion or multi-cell alkaline systems. |
| Quiescent Current | <2 µA in shutdown mode; extends battery life in always-on standby circuits such as real-time clocks or sensor wake-up monitors. |
| Power-On Reset Delay | Programmable via external capacitor on DELAY pin (CDLY = TDELAY / 5.59×10⁵); supports configurable system initialization timing without additional ICs. |
| Ground Pin Current | 1 mA @ 200 mA load (typical); low parasitic current minimizes total system power loss and improves efficiency in low-power embedded designs. |
| Operating Junction Temp | −40°C to +125°C; validated for automotive cabin modules, industrial handhelds, and outdoor-connected devices without derating. |
| Input Voltage Range | 2.1 V to 16 V (operating); accommodates wide-input DC-DC pre-regulation stages or unregulated wall adapters with transient headroom. |
Pinout & Package
VSSOP-8 (DGK) package: 3.0 mm × 3.0 mm, 0.65 mm pitch, exposed thermal pad (not electrically connected), RoHS-compliant matte tin lead finish, MSL Level-1 (unlimited floor life).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - BYPASS | Not connected (NC) | This pin is unused on LP2987; differs from LP2988 which uses it for noise reduction-no external capacitor required. |
| 2 - DELAY | Reset delay timing node | Sinks 2.2 µA current to charge external capacitor; sets power-on reset timeout-enables deterministic firmware boot sequencing. |
| 3 - GROUND | Analog ground reference | Return path for internal bias and error amplifier; must connect to clean analog ground plane to avoid noise coupling into regulation loop. |
| 4 - INPUT | Unregulated input supply | Accepts 2.1–16 V; requires ≥2.2 µF input capacitor within 0.5″ to suppress high-frequency ripple and prevent instability. |
| 5 - SENSE | Output voltage feedback | Monitors regulated output directly; enables remote sensing to compensate for PCB trace IR drop in high-current applications. |
| 6 - OUTPUT | Regulated 5.0 V output | Delivers up to 200 mA; requires ≥4.7 µF output capacitor with ESR in stable region per TI Figure 44 to prevent oscillation. |
| 7 - SHUTDOWN | Enable/disable control | Active-high logic input; drives high (>1.6 V) to enable, low (<0.18 V) to enter sub-2 µA shutdown-supports host MCU power gating. |
| 8 - ERROR | Open-collector reset flag | Asserts low during undervoltage or startup; requires external pull-up resistor to define logic-high level and drive downstream reset inputs. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low dropout | 180 mV @ 200 mA enables use with marginal input sources (e.g., aging batteries or post-buck converter rails) without losing regulation. |
| Programmable reset delay | Single external capacitor on DELAY pin eliminates need for discrete RC timers or dedicated supervisor ICs in space-constrained designs. |
| 0.5% output accuracy (A-grade) | Tight tolerance ensures reliable operation of 5 V-tolerant I/O peripherals and ADC references without calibration overhead. |
| Thermal/overcurrent protection | Internally limits power dissipation and shuts down on fault-prevents damage during short-circuit or overload events without external circuitry. |
| Low ground pin current | 1 mA @ 200 mA load reduces total system current draw versus legacy LDOs, improving battery runtime in portable electronics. |
Applications
| Cellular Phone Power Management | Palmtop Computer Core Rail |
|---|---|
|
Use Scenario: Supplies 5 V to baseband processor I/O banks and USB PHY during active call mode with dynamic load steps up to 200 mA. IC Role / Device Role / Timing Role: Primary low-noise, low-dropout post-regulator delivering stable 5 V from switched-mode DC-DC output. Use Value: 180 mV dropout preserves headroom under battery discharge; 0.5% accuracy prevents I/O timing violations; ERROR pin synchronizes modem reset with power rail stabilization. |
Use Scenario: Powers FPGA configuration memory and display interface logic in clamshell-form factor palmtops with tight thermal envelopes. IC Role / Device Role / Timing Role: Fixed 5 V LDO providing clean, sequenced supply with programmable reset delay matching FPGA configuration timing requirements. Use Value: DELAY pin capacitor configures 100 ms reset hold time; VSSOP-8 footprint saves board area; thermal shutdown protects against localized hot spots near display driver ICs. |
| Camcorder Audio Codec Supply | Personal Stereo DAC Reference Rail |
|
Use Scenario: Delivers ultra-stable 5 V to audio codec's analog section during video recording, rejecting switching noise from adjacent DC-DC converters. IC Role / Device Role / Timing Role: Low-noise linear regulator isolating sensitive analog circuitry from noisy digital domains using SENSE pin for remote sensing. Use Value: 100 µVRMS output noise (vs. 20 µVRMS for LP2988) meets SNR requirements for 16-bit audio; SENSE connection compensates for 50 mΩ PCB trace resistance. |
Use Scenario: Provides precision 5 V reference to stereo DAC in battery-powered personal audio players, operating across −10°C to +50°C ambient. IC Role / Device Role / Timing Role: High-accuracy, temperature-stable LDO ensuring consistent DAC full-scale output regardless of battery voltage sag or thermal drift. Use Value: ±0.5% output tolerance and 20 ppm/°C tempco maintain DAC linearity; −40°C to +125°C rating covers extended consumer temperature range with margin. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar LDO regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LP2987IMX-5.0/NOPB | SOIC-8 package (larger footprint, 160°C/W θJ−A), same electrical specs and pinout. | Better thermal performance at high ambient temperatures; suited for through-hole prototyping or legacy board rework. | Select when board layout allows SOIC-8 and thermal design prioritizes lower junction rise over size. |
| LP2988AIMM-5.0/NOPB | Includes BYPASS pin and achieves 20 µVRMS output noise (vs. 100 µVRMS); otherwise identical pinout and regulation specs. | Required for ultra-low-noise analog signal chains (e.g., high-fidelity audio, precision ADCs) where 5× noise reduction is critical. | Choose only if noise specification mandates <30 µVRMS; otherwise LP2987AIMM-5.0/NOPB offers cost and footprint advantage. |
Compared with LP2987IMX-5.0/NOPB, the LP2987AIMM-5.0/NOPB saves 40% board area but requires more aggressive thermal copper; versus LP2988AIMM-5.0/NOPB, it trades 5× higher output noise for lower unit cost and simplified BOM-ideal for digital I/O and non-audio analog rails.
Availability
LP2987AIMM-5.0/NOPB is available at Aetrix Electronics and suitable for cellular phone power management, palmtop computer core rails, camcorder audio codec supplies, and personal stereo DAC reference rails requiring stable component supply across industrial temperature ranges and long production lifecycles.
Supply support for LP2987AIMM-5.0/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of LDO design heritage and broad automotive/industrial qualification.
The LP2987 series was engineered for micropower, ultra-low-dropout regulation in portable electronics-emphasizing minimal quiescent current, precise output accuracy, and integrated power-on reset functionality without external components.
FAQ
What is the maximum continuous output current for LP2987AIMM-5.0/NOPB?
The LP2987AIMM-5.0/NOPB is specified for continuous output current up to 200 mA under recommended thermal conditions. Peak output current exceeds 250 mA, but sustained operation above 200 mA requires careful thermal design due to the VSSOP-8 package's 200°C/W junction-to-ambient resistance-derating is necessary above 85°C ambient.
Does LP2987AIMM-5.0/NOPB require an external bypass capacitor?
No, LP2987AIMM-5.0/NOPB does not use the BYPASS pin-it is a no-connect (NC) terminal. Unlike the LP2988 variant, this device lacks the internal circuitry that benefits from a bypass capacitor; its output noise is 100 µVRMS, and stability relies solely on proper input/output capacitor selection per TI's ESR guidelines.
How is the power-on reset delay configured on LP2987AIMM-5.0/NOPB?
The power-on reset delay on LP2987AIMM-5.0/NOPB is set by connecting an external capacitor between the DELAY pin and ground. The delay time (TDELAY) follows CDLY = TDELAY / 5.59×10⁵, supporting delays from ~10 ms to 1 s. A 100 nF capacitor yields ~56 ms delay-ideal for synchronizing microcontroller boot with power rail stabilization.
What is the shutdown behavior of LP2987AIMM-5.0/NOPB?
LP2987AIMM-5.0/NOPB enters ultra-low-power shutdown when the SHUTDOWN pin voltage falls below 0.18 V (max), drawing less than 2 µA quiescent current. To enable regulation, the pin must be driven above 1.6 V (min). The input must slew at ≥40 mV/µs to avoid metastability-direct connection to a GPIO or pull-up to VIN is recommended.
Can LP2987AIMM-5.0/NOPB be used with ceramic output capacitors?
Yes, LP2987AIMM-5.0/NOPB supports ceramic output capacitors, but a 1 Ω series resistor is required to ensure stability-ceramic ESR can fall below the minimum stable range (e.g., 15 mΩ for 2.2 µF), risking oscillation. Tantalum capacitors (≥4.7 µF, low-ESR grade) are preferred for guaranteed stability without added components.
LP2987AIMM-5.0/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 8-TSSOP, 8-MSOP (0.118", 3.00mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 16V
- Voltage - Output (Min/Fixed):
- 5V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.35V @ 200mA
- Current - Output:
- 200mA
- Current - Quiescent (Iq):
- 120 µA
- Current - Supply (Max):
- 3.7 mA
- PSRR:
- 65dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Short Circuit
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSSOP
LP2987AIMM-5.0/NOPB FAQ
1.How can I place an order for LP2987AIMM-5.0/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP2987AIMM-5.0/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP2987AIMM-5.0/NOPB reliable?
The price and inventory of LP2987AIMM-5.0/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP2987AIMM-5.0/NOPB is usually 5 days.
3.What payment methods are accepted for LP2987AIMM-5.0/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP2987AIMM-5.0/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP2987AIMM-5.0/NOPB?
LP2987AIMM-5.0/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP2987AIMM-5.0/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP2987AIMM-5.0/NOPB?
For technical support, including LP2987AIMM-5.0/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP2987AIMM-5.0/NOPB requirements.
6.How does Aetrix verify that LP2987AIMM-5.0/NOPB is sourced from the original manufacturer or authorized distributors?
All LP2987AIMM-5.0/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP2987AIMM-5.0/NOPB meets industry standards.
7.What is the process for return or replacement of LP2987AIMM-5.0/NOPB?
All LP2987AIMM-5.0/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP2987AIMM-5.0/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP2987AIMM-5.0/NOPB part is unused and in its original packaging.
Return procedure for LP2987AIMM-5.0/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LP2987AIMM-5.0/NOPB Tags
-
MIC5504-1.8YM5-TR
Microchip Technology
-
MIC5504-3.3YM5-TR
Microchip Technology
-
MIC5365-3.0YC5-TR
Microchip Technology
-
MIC5365-1.8YC5-TR
Microchip Technology
-
MIC5365-2.5YC5-TR
Microchip Technology
-
MIC5365-3.3YC5-TR
Microchip Technology
-
MIC5365-3.3YD5-TR
Microchip Technology
-
MIC5317-3.3YM5-TR
Microchip Technology
-
TLV1117LV33DCYR
Texas Instruments
-
MIC5317-3.3YMT-TZ
Microchip Technology
-
MIC5528-3.3YMT-TR
Microchip Technology
-
TLV75801PDRVR
Texas Instruments
Tech Hub
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
LDO regulator guide covering low dropout voltage, power dissipation, thermal design, PSRR, output noise, capacitor stability, adjustable LDO circuits, LDO vs buck converter and datasheet selection chec…
Conditional Access Module guide covering CAM meaning, CI/CI+ interface, smart card authorization, DVB security workflow, TV and set-top box compatibility, internal electronics, ESD protection, connecto…
Guide to electronic component obsolescence covering EOL risk, PCN/PDN notices, last-time buy planning, replacement options, form-fit-function validation, counterfeit risk and BOM lifecycle management.
18650 battery guide covering lithium-ion cell basics, 3.6V/3.7V voltage, 4.2V charging, mAh and Wh capacity, protected cells, chargers, BMS, series-parallel packs, holders, welding and sourcing checks.…
