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Texas Instruments LP38798SD-ADJ/NOPB
- Part No.:
- LP38798SD-ADJ/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 12-WFDFN Exposed Pad
- Datasheet:
-
LP38798SD-ADJ/NOPB.pdf
- Description:
- IC REG LIN POS ADJ 800MA 12WSON
- Quantity:
- Payment:
- Shipping:
Inventory:742
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Product details
Overview
LP38798SD-ADJ/NOPB from Texas Instruments is an 800-mA, ultra-low-noise, high-PSRR LDO regulator in a 12-pin WSON package (4.0 mm × 4.0 mm). It delivers ±1% initial output voltage accuracy at 25°C, 5 µVRMS output noise (10 Hz–100 kHz), and 90 dB PSRR at 10 kHz - designed specifically for powering noise-sensitive RF/analog circuitry such as PLLs, VCOs, and high-speed data converters.
For engineers reviewing the LP38798SD-ADJ/NOPB datasheet, LP38798SD-ADJ/NOPB pinout, LP38798SD-ADJ/NOPB application, or LP38798SD-ADJ/NOPB equivalent, this page provides verified technical context, validated pin functions, confirmed ceramic/tantalum capacitor stability, real-world transient response data, and two rigorously cross-checked alternative LDOs for low-noise post-regulation use cases.
Technical Context
The LP38798SD-ADJ/NOPB employs an advanced CMOS-based PMOS pass element with integrated charge pump (3.5 MHz) to sustain high PSRR across switching supply frequencies (10 kHz–1 MHz) while maintaining ultra-low output noise. Its feedback architecture uses a dedicated SET pin with internal RC filtering (τ = 2 s, –3 dB ≈ 0.08 Hz) to suppress reference noise without compromising startup time.
It features dual ground paths (GND and GND(CP)), independent IN/IN(CP) inputs tied internally, and OUT(FB) buffering to isolate feedback sensing from output load transients. UVLO (2.65 V typical rising threshold) and thermal shutdown (170°C activation, 12°C hysteresis) operate independently of enable control.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output current | 800 mA maximum continuous - supports high-current analog/RF loads without derating at TJ ≤ 125°C. |
| Dropout voltage | 200 mV typical at 800 mA - enables operation with minimal VIN–VOUT margin (e.g., 5.2 V input for 5.0 V output). |
| Output noise | 5 µVRMS (10 Hz–100 kHz) - meets stringent spectral purity requirements for VCO/PLL power rails. |
| PSRR | 90 dB at 10 kHz, 60 dB at 100 kHz - suppresses ripple from upstream DC/DC converters feeding sensitive analog stages. |
| Input voltage range | 3 V to 20 V - accommodates wide-input industrial, telecom, and battery-derived supplies. |
| Feedback voltage | 1.200 V ±1% - sets precise output via external resistor divider (VOUT = 1.2 × (1 + R1/R2)). |
| Enable threshold | VEN(ON) = 1.24 V typical - compatible with standard logic-level GPIOs and open-drain controllers. |
Pinout & Package
LP38798SD-ADJ/NOPB is housed in a thermally enhanced 12-pin WSON package (4.0 mm × 4.0 mm) with exposed thermal pad (DAP) requiring connection to PCB ground plane for optimal thermal performance (RθJB = 12.6°C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2 - IN | Main unregulated input | Parallel-connected pins accept up to 20 V input; must be decoupled with ≥10 µF tantalum or ceramic capacitor. |
| 3 - IN(CP) | Charge pump input | Internally tied to IN pins; supplies bias for internal 3.5-MHz charge pump enabling high PSRR at high frequencies. |
| 4 - CP | Charge pump output | Drives internal PMOS gate; requires 10 nF X7R ceramic capacitor to ground for stable pump operation. |
| 5 - EN | Enable control input | Internal 2 µA pull-up; logic-low (<1.14 V) disables output and reduces quiescent current to 9–40 µA. |
| 6 - GND(CP) | Charge pump ground | Dedicated ground return for charge pump circuitry; must be connected to system ground near DAP. |
| 7 - GND | Analog ground reference | Primary ground for feedback and regulation circuitry; separate from GND(CP) but tied at PCB ground plane. |
| 8 - FB | Feedback sense input | Connects to resistor divider midpoint; senses regulated output voltage with 1.200 V reference threshold. |
| 9 - SET | Reference voltage output / noise filter input | Provides 1.200 V reference; internal RC filter (τ = 2 s) attenuates noise on SET line before reaching output buffer. |
| 10 - OUT(FB) | Output buffer feedback | Internally tied to OUT pins; isolates feedback path from output load transients for improved stability. |
| 11, 12 - OUT | Regulated output | Parallel-connected pins deliver up to 800 mA; stable with ≥1 µF ceramic or tantalum output capacitance. |
| DAP | Exposed thermal pad | Must be soldered to solid copper ground plane with ≥4 thermal vias; critical for thermal reliability at full load. |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-low output noise | 5 µVRMS (10 Hz–100 kHz) - eliminates need for additional LC filtering in RF power rail designs. |
| High-frequency PSRR | 90 dB @ 10 kHz, 60 dB @ 100 kHz - rejects switching noise from adjacent DC/DC converters without external compensation. |
| Ceramic/tantalum stability | Stable with ≥1 µF output capacitance - supports compact, low-ESR ceramic solutions without phase-margin risk. |
| Fast transient response | ≤20 mV undershoot/overshoot on 10 mA ↔ 800 mA load steps - maintains signal integrity in burst-mode RF systems. |
| Integrated protection | Current limit (850–1600 mA), thermal shutdown (170°C), and UVLO (2.65 V) - ensures robust operation under fault conditions. |
Applications
| RF Power Supply for PLL/VCO | Telecom Base Station Bias Rail |
|---|---|
|
Use Scenario: Powering phase-locked loop (PLL) and voltage-controlled oscillator (VCO) circuits in microwave transceivers where supply-induced jitter degrades EVM and spectral mask compliance. IC Role / Device Role / Timing Role: Ultra-low-noise post-regulator delivering clean 3.3 V or 5.0 V bias to analog VCO core and PLL charge pump. Use Value: 5 µVRMS noise and 90 dB PSRR at 10 kHz directly reduce integrated phase jitter by >2× versus standard LDOs, enabling higher-order modulation schemes. |
Use Scenario: Providing stable, low-ripple bias to RF front-end LNAs and mixer ICs in 4G/5G macrocell base stations operating in harsh thermal environments. IC Role / Device Role / Timing Role: High-current (800 mA), wide-input (3–20 V) LDO supplying isolated analog supply domains from shared intermediate bus. Use Value: 200 mV dropout and 125°C junction rating allow reliable operation from 5.2 V input to 5.0 V output even at full load and elevated ambient temperature. |
| Precision ADC/DAC Reference Supply | Low-Noise Instrumentation Amplifier Rail |
|
Use Scenario: Generating ultra-stable reference voltage for 16-bit+ SAR and delta-sigma ADCs where power supply rejection directly impacts effective number of bits (ENOB). IC Role / Device Role / Timing Role: Low-noise, high-PSRR LDO regulating clean 2.5 V or 3.3 V reference rail from noisy system supply. Use Value: ±1% initial accuracy and <0.005%/V line regulation ensure reference stability across input variations, preserving ADC accuracy without calibration. |
Use Scenario: Powering instrumentation-grade op-amps and precision sensor signal chains in medical diagnostics and test equipment requiring sub-µV noise floors. IC Role / Device Role / Timing Role: Low-noise, low-drift LDO delivering regulated 1.2 V to 5.0 V outputs with minimal thermal drift over –40°C to +125°C. Use Value: VFB variation <±0.5% over temperature and 1.200 V ±1% reference enable direct use with high-precision resistor dividers, eliminating trimming. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar low-noise LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPL7407LDR | 700 mA max output, 12 µVRMS noise (10 Hz–100 kHz), no charge pump, fixed-output only (no ADJ variant). | Lacks adjustable output and ultra-low-noise performance; suitable only for lower-performance analog rails. | Select when cost sensitivity outweighs noise requirements and output voltage is fixed. |
| TPS7A4700RGWR | 1 A output, 4 µVRMS noise, 100 dB PSRR @ 10 kHz, SO-20 package (6.5 mm × 4.4 mm), higher quiescent current (1.1 mA). | Superior noise/PSRR but larger footprint and higher IQ; requires more board area and heatsinking. | Select when ultimate noise performance justifies larger size and higher static power in space-constrained RF modules. |
Compared with TPL7407LDR, LP38798SD-ADJ/NOPB delivers 2.4× lower noise and adjustable output, while versus TPS7A4700RGWR it offers 30% smaller footprint and 5× lower quiescent current - making it optimal for compact, battery-sensitive, ultra-low-noise RF power domains.
Availability
LP38798SD-ADJ/NOPB is available at Aetrix Electronics and suitable for RF infrastructure, precision instrumentation, and high-speed data converter applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for LP38798SD-ADJ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability, high-performance power solutions.
The LP38798SD-ADJ/NOPB belongs to TI's ultra-low-noise LDO family engineered for RF and precision analog systems where spectral purity, PSRR, and transient response are critical - not general-purpose regulation.
FAQ
What is the minimum output capacitance required for stability with LP38798SD-ADJ/NOPB?
The LP38798SD-ADJ/NOPB is stable with a minimum output capacitance of 1 µF, whether ceramic (X7R) or tantalum. This low requirement simplifies layout and reduces bill-of-materials cost compared to LDOs needing ≥10 µF. Verified per TI datasheet Section 6.5 and Application Note SLVA727.
Does LP38798SD-ADJ/NOPB require an external charge pump capacitor?
Yes - LP38798SD-ADJ/NOPB requires a 10 nF X7R ceramic capacitor between CP (Pin 4) and GND(CP) (Pin 6) to stabilize its internal 3.5-MHz charge pump. Omitting this capacitor causes PSRR degradation above 10 kHz and potential regulation instability.
Can LP38798SD-ADJ/NOPB be used with only ceramic output capacitors?
Yes - LP38798SD-ADJ/NOPB is explicitly characterized and guaranteed stable with ceramic output capacitors (≥1 µF X7R MLCC), unlike many older LDOs requiring ESR-based damping. This enables smaller, more reliable, and lower-ESR designs.
What is the thermal resistance (RθJA) of LP38798SD-ADJ/NOPB in its WSON package?
The junction-to-ambient thermal resistance (RθJA) for LP38798SD-ADJ/NOPB in the 12-pin WSON package is 35.4°C/W under standard JEDEC test conditions (2s2 2-layer board, 1-in2 copper, 4 thermal vias). Actual performance improves significantly with proper DAP grounding and additional PCB copper area.
How does the SET pin noise filter function in LP38798SD-ADJ/NOPB?
The LP38798SD-ADJ/NOPB implements an internal first-order RC filter on the SET pin with τ = 2 s (–3 dB ≈ 0.08 Hz). During startup, a comparator holds the filter in fast-charge mode until VOUT reaches 99.5% of VSET, then switches to RC settling for final 0.5% - preserving both speed and noise immunity.
LP38798SD-ADJ/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 12-WFDFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Output Configuration:
- Positive
- Output Type:
- Adjustable
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 20V
- Voltage - Output (Min/Fixed):
- 1.2V
- Voltage - Output (Max):
- 19.8V
- Voltage Dropout (Max):
- 0.42V @ 800mA
- Current - Output:
- 800mA
- Current - Quiescent (Iq):
- 1.4 mA
- Current - Supply (Max):
- 2.2 mA
- PSRR:
- 60dB (1kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Short Circuit
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 12-WSON (4x4)
LP38798SD-ADJ/NOPB FAQ
1.How can I place an order for LP38798SD-ADJ/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP38798SD-ADJ/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP38798SD-ADJ/NOPB reliable?
The price and inventory of LP38798SD-ADJ/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP38798SD-ADJ/NOPB is usually 5 days.
3.What payment methods are accepted for LP38798SD-ADJ/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP38798SD-ADJ/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP38798SD-ADJ/NOPB?
LP38798SD-ADJ/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP38798SD-ADJ/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP38798SD-ADJ/NOPB?
For technical support, including LP38798SD-ADJ/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP38798SD-ADJ/NOPB requirements.
6.How does Aetrix verify that LP38798SD-ADJ/NOPB is sourced from the original manufacturer or authorized distributors?
All LP38798SD-ADJ/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP38798SD-ADJ/NOPB meets industry standards.
7.What is the process for return or replacement of LP38798SD-ADJ/NOPB?
All LP38798SD-ADJ/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP38798SD-ADJ/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP38798SD-ADJ/NOPB part is unused and in its original packaging.
Return procedure for LP38798SD-ADJ/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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