Texas Instruments LP38798SDE-ADJ/NOPB

Overview

LP38798SDE-ADJ/NOPB from Texas Instruments is an 800-mA, ultra-low-noise (5 µV_RMS), high-PSRR (90 dB @ 10 kHz) adjustable LDO regulator in a 12-pin WSON package. It operates from 3 V to 20 V input, delivers ±1% initial output accuracy at 25°C, and maintains stability with ≥1 µF ceramic or tantalum output capacitors - ideal for powering RF-sensitive analog circuitry such as PLLs and high-speed ADCs.

For engineers reviewing the LP38798SDE-ADJ/NOPB datasheet, LP38798SDE-ADJ/NOPB pinout, LP38798SDE-ADJ/NOPB application, or LP38798SDE-ADJ/NOPB equivalent, key selection criteria include dropout voltage (200 mV typ. @ 800 mA), noise performance across 10 Hz–100 kHz, PSRR behavior at SMPS frequencies, and compatibility with low-ESR ceramic output caps without external compensation.

Technical Context

The LP38798SDE-ADJ/NOPB employs an advanced CMOS-based PMOS pass element with integrated charge pump (3.5 MHz) to sustain regulation at low dropout while enabling high PSRR up to 100 kHz. Its feedback architecture uses a precision 1.200 V internal reference and supports external resistor programming via SET/FB pins for adjustable output voltages from 1.2 V to (VIN – V_DO).

It integrates active ripple rejection, UVLO (2.65 V rising threshold), thermal shutdown (170°C), and current limiting (850–1600 mA). The internal noise filter on the SET pin features a 2-second RC time constant and fast-charge mode to preserve start-up response while suppressing broadband noise injection into the output buffer.

Key Specifications

Pinout & Package

LP38798SDE-ADJ/NOPB is housed in a thermally enhanced 12-pin WSON package (4.00 mm × 4.00 mm) with exposed die attach pad (DAP) that must be connected to PCB ground for optimal thermal performance.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar LDO regulator applications.

Compared with TPL7407LPGQ and TPS7A4700RGWR, the LP38798SDE-ADJ/NOPB offers the optimal balance of 800-mA capability, 5-µV noise, 20-V input support, and compact 4-mm WSON footprint - making it uniquely suited for space-constrained RF and precision analog designs where both performance and integration matter.

Availability

LP38798SDE-ADJ/NOPB is available at Aetrix Electronics and suitable for RF infrastructure, precision instrumentation, and high-speed data converter applications requiring stable component supply, long-term manufacturability, and guaranteed lot traceability.

Supply support for LP38798SDE-ADJ/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader delivering analog and embedded processing solutions, with decades of expertise in power management IC design and high-reliability manufacturing.

The LP38798SDE-ADJ/NOPB belongs to TI's ultra-low-noise LDO portfolio, engineered specifically for noise-sensitive RF, analog, and precision timing applications where conventional regulators introduce unacceptable spectral contamination.

FAQ

What is the minimum output capacitance required for stability with LP38798SDE-ADJ/NOPB?

The LP38798SDE-ADJ/NOPB is stable with a minimum 1 µF ceramic or tantalum output capacitor. This low requirement simplifies layout and reduces bill-of-materials cost compared to legacy LDOs needing ≥10 µF. Verified across temperature and load conditions per TI SNOSCT6F datasheet Section 6.5.

Does LP38798SDE-ADJ/NOPB require an external charge pump capacitor?

Yes - LP38798SDE-ADJ/NOPB requires a 10 nF X7R ceramic capacitor between CP (pin 4) and GND(CP) (pin 6). This capacitor stabilizes the internal 3.5-MHz charge pump that drives the PMOS pass transistor gate, ensuring consistent low-dropout performance across load and input conditions.

How does the SET pin noise filter function in LP38798SDE-ADJ/NOPB?

The LP38798SDE-ADJ/NOPB implements an internal first-order RC filter on the SET pin with τ ≈ 2 seconds and a –3-dB point near 0.08 Hz. During start-up, a comparator places it in fast-charge mode until VOUT reaches 99.5% of VSET, then reverts to filtered operation - preserving low noise without compromising rise time.

What is the thermal performance of LP38798SDE-ADJ/NOPB in its WSON package?

With proper PCB layout (DAP soldered to ≥100 mm² GND copper area and ≥4 thermal vias), LP38798SDE-ADJ/NOPB achieves R_θJA = 35.4°C/W and R_θJB = 12.6°C/W. At 800 mA and 5 V drop, junction temperature rise is ~28°C above ambient - well below the 125°C max operating limit and 170°C thermal shutdown threshold.

Can LP38798SDE-ADJ/NOPB be used with input voltages below 3 V?

No - LP38798SDE-ADJ/NOPB incorporates undervoltage lockout (UVLO) with a typical rising threshold of 2.65 V and hysteresis of 180 mV. Operation below 2.47 V (min UVLO) is not functional; the device remains disabled. The recommended operating range starts at 3 V per datasheet Section 6.3.