Texas Instruments LP3907QSQX-JXI7/NOPB
- Part No.:
- LP3907QSQX-JXI7/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 24-WFQFN Exposed Pad
- Datasheet:
-
LP3907QSQX-JXI7/NOPB.pdf
- Description:
- IC REG QUAD BUCK/LNR SYNC 24WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LP3907QSQX-JXI7/NOPB from Texas Instruments is a programmable power management IC integrating two synchronous buck converters (1 A and 600 mA), two 300-mA LDOs, and an I²C interface - all in a single WQFN-24 package. It delivers precision voltage regulation for FPGA/DSP core and I/O rails, supports dynamic voltage scaling, and features programmable power-on sequencing with external nPOR control.
For engineers reviewing the LP3907QSQX-JXI7/NOPB datasheet, LP3907QSQX-JXI7/NOPB pinout, LP3907QSQX-JXI7/NOPB application, or LP3907QSQX-JXI7/NOPB equivalent, this device serves as a compact, I²C-configurable PMU for battery-powered portable electronics requiring multi-rail sequencing, high light-load efficiency via PWM-to-PFM mode, and ±3% output accuracy across temperature.
Technical Context
The LP3907QSQX-JXI7/NOPB implements two independent synchronous buck regulators with 2.1-MHz fixed-frequency PWM operation and automatic transition to PFM mode under light loads - maintaining >90% efficiency down to 1 mA. Its dual LDOs use PMOS pass devices with 30-mV typical dropout and support 1 V–3.5 V programmable outputs.
Control is fully managed via a 400-kHz I²C interface (7-bit address 0x3C for WQFN packages), enabling real-time register access for voltage setting, enable/disable sequencing, power-good monitoring, and thermal/overcurrent fault reporting. The device includes integrated undervoltage lockout (2.7 V–2.9 V), thermal shutdown (160°C), and soft-start circuitry for both bucks and LDOs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.8 V to 5.5 V - supports single-cell Li-ion, USB, or regulated 3.3 V/5 V supplies without external pre-regulation. |
| Buck1 Output | 0.8 V–2.0 V at 1 A - programmable for FPGA core voltages with ±3% accuracy and 2.1-MHz switching. |
| Buck2 Output | 1.0 V–3.5 V at 600 mA - configurable for I/O or peripheral rails; enters PFM mode below ~10 mA load. |
| LDO1/LDO2 Output | 1.0 V–3.5 V at 300 mA each - low-noise (80 µVrms), low-dropout (30 mV typ) linear regulation with independent enable pins. |
| I²C Interface | 400-kHz standard-mode - enables host microcontroller to configure all rails, monitor status, and manage sequencing via 7-bit address 0x3C. |
| Package | WQFN-24 (4.0 mm × 4.0 mm, 0.5-mm pitch) - thermally enhanced with exposed DAP for PCB heat dissipation. |
| Thermal Protection | Thermal shutdown at 160°C (typ), hysteresis 20°C - prevents permanent damage during sustained overload or poor airflow. |
Pinout & Package
LP3907QSQX-JXI7/NOPB uses the RTW WQFN-24 package (4.0 mm × 4.0 mm, 0.5-mm pitch) with an exposed thermal pad (DAP) recommended for soldering to improve thermal performance. Pin numbering follows standard top-view orientation with Pin 1 at bottom-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VINLDO12 | Analog power supply | Provides 2.8–5.5 V bias for internal reference, I²C logic, and control circuitry - must be decoupled with 1 µF ceramic capacitor. |
| EN_T | Sequencing enable input | Active-high logic input that initiates preset power-on sequence; ties to system enable signal or microcontroller GPIO. |
| nPOR | Open-drain power-good output | Asserts low when Buck1/Buck2 outputs fall below 85% of target; requires external 100-kΩ pullup for system reset coordination. |
| SW1 / SW2 | Buck switch node outputs | Connect to external 2.2-µH inductors and 10-µF output capacitors; high dv/dt nodes requiring tight layout and ground shielding. |
| FB1 / FB2 | Voltage feedback inputs | Resistive divider inputs (typically 100 kΩ/100 kΩ) for precise output voltage programming; high-impedance analog sensing nodes. |
| LDO1 / LDO2 | Linear regulator outputs | Deliver low-noise, low-dropout power to sensitive analog or digital circuits; require 0.47–1 µF ceramic output capacitors. |
| SDA / SCL | I²C bidirectional data/clock | Standard 400-kHz I²C interface; require 4.7-kΩ pullups to AVDD; support multi-device bus sharing with unique 7-bit address. |
Key Features
| Feature | Design Value |
|---|---|
| Dynamic Voltage Scaling (DVS) | Independent I²C-controlled adjustment of Buck1/Buck2 output voltages during operation - enables FPGA core frequency scaling and power optimization. |
| PWM-to-PFM Light-Load Mode | Automatic transition below ~10 mA load reduces quiescent current to 33 µA and maintains >85% efficiency - critical for battery runtime in standby. |
| Programmable Power-On Sequencing | Configurable delay and order between Buck1, Buck2, LDO1, and LDO2 via internal registers - eliminates need for external sequencer ICs. |
| Integrated Power-Good Monitoring | nPOR open-drain output signals valid regulation of both bucks simultaneously - simplifies system-level reset timing and fault detection. |
| Low-Noise LDO Regulation | 80 µVrms output noise and 45 dB PSRR at 10 kHz - suitable for powering ADC references, RF synthesizers, or audio codecs without added filtering. |
Applications
| FPGA Core & I/O Power | DSP Processor Supply |
|---|---|
Use Scenario: Powering Xilinx Spartan or Intel Cyclone FPGA with separate 1.2-V core and 3.3-V I/O rails. IC Role / Device Role / Timing Role: LP3907QSQX-JXI7/NOPB provides tightly regulated, sequenced, and dynamically scalable voltage rails via I²C commands from FPGA configuration controller. Use Value: Eliminates discrete DC-DC + LDO combinations; reduces BOM count by 4+ components while enabling runtime voltage adaptation for power gating. |
Use Scenario: Supplying TI C6000 DSP with 1.4-V core and 3.3-V peripheral interface in portable medical imaging equipment. IC Role / Device Role / Timing Role: LP3907QSQX-JXI7/NOPB delivers low-noise, low-dropout power with programmable startup delays to meet DSP boot timing requirements. Use Value: Achieves <100-µs LDO turn-on time and ±3% output stability over –40°C to +85°C - ensures deterministic DSP initialization. |
| Portable Hearing Aid System | Electronic Measurement Unit |
Use Scenario: Multi-rail power for ultra-low-power ARM Cortex-M0+ MCU, MEMS microphone, and Class-D audio amplifier in rechargeable hearing aids. IC Role / Device Role / Timing Role: LP3907QSQX-JXI7/NOPB manages battery-efficient sequencing of 1.8-V MCU, 2.8-V sensor, and 3.3-V amplifier rails using I²C-triggered enable states. Use Value: Delivers 33 µA quiescent current in PFM mode and 30-mV LDO dropout - extends single-charge runtime beyond 120 hours. |
Use Scenario: Precision analog front-end (AFE) and microcontroller supply in handheld multimeters or environmental sensors. IC Role / Device Role / Timing Role: LP3907QSQX-JXI7/NOPB powers 2.5-V ADC reference (via LDO2) and 3.3-V MCU (via Buck2) with independent enable control and nPOR coordination. Use Value: Provides 80 µVrms LDO noise and 45 dB PSRR - preserves 16-bit ADC ENOB without additional ferrite beads or LC filters. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Triple buck (2×1.5 A, 1×1 A) + dual LDO (2×200 mA); no DVS; I²C address fixed at 0x2D. | Lacks dynamic voltage scaling and has lower LDO current capability - suitable only for static rail systems. | Select when fixed-voltage rails and higher buck current are prioritized over programmability and LDO headroom. |
| MAX8649ETG+ | Dual buck (1.2 A/600 mA) + triple LDO (3×300 mA); 1.8-MHz switching; no nPOR output. | Missing dedicated power-good signaling - requires external supervisor IC for system reset coordination. | Choose when needing third LDO rail and tighter footprint (3×3 mm TQFN), accepting added complexity for POR functionality. |
Compared with TPS65023RSBR and MAX8649ETG+, the LP3907QSQX-JXI7/NOPB uniquely combines DVS, integrated nPOR, and matched 300-mA LDOs in a thermally optimized WQFN - making it optimal for space-constrained, battery-operated systems requiring adaptive power management.
Availability
LP3907QSQX-JXI7/NOPB is available at Aetrix Electronics and suitable for FPGA core power, DSP processor supply, and portable hearing aid systems requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for LP3907QSQX-JXI7/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies - with over 50 years of innovation in high-reliability, energy-efficient IC design.
The LP3907QSQX-JXI7/NOPB belongs to TI's Power Management Unit (PMU) product line, engineered specifically for low-power portable electronics requiring compact, I²C-programmable multi-rail power with sequencing and dynamic voltage scaling.
FAQ
What is the default I²C address for LP3907QSQX-JXI7/NOPB?
The LP3907QSQX-JXI7/NOPB uses the WQFN-24 (RTW) package, which has a default I²C 7-bit address of 0x3C (hex). This address is factory-programmed and cannot be changed. Communication occurs at up to 400 kHz in standard-mode I²C, and the device supports repeated start conditions per its timing specifications.
Does LP3907QSQX-JXI7/NOPB support dynamic voltage scaling for both buck converters?
Yes, LP3907QSQX-JXI7/NOPB supports independent dynamic voltage scaling (DVS) for both Buck1 and Buck2 via I²C register writes. Each buck's output voltage can be adjusted in real time across its full range (Buck1: 0.8–2.0 V; Buck2: 1.0–3.5 V), enabling runtime optimization of FPGA or DSP core performance and power consumption.
What is the maximum allowable input voltage for the LDO inputs on LP3907QSQX-JXI7/NOPB?
The LDO input pins (VINLDO1 and VINLDO2) of LP3907QSQX-JXI7/NOPB support an operational voltage range of 1.74 V to 5.5 V. This extended low-end rating allows direct connection to buck converter outputs (e.g., 1.8 V or 2.5 V rails) without intermediate regulation - a key feature confirmed in the "Power Block" section of the datasheet.
How does the nPOR function work on LP3907QSQX-JXI7/NOPB?
The nPOR pin on LP3907QSQX-JXI7/NOPB is an open-drain output that asserts low when either Buck1 or Buck2 output falls below 85% of its programmed value. It releases (goes high-impedance) only after both outputs exceed 94% of target. An external 100-kΩ pullup to AVDD is required to generate a clean system reset signal synchronized to power rail stability.
What thermal considerations apply to LP3907QSQX-JXI7/NOPB in continuous 1-A operation?
In continuous 1-A operation at Buck1, LP3907QSQX-JXI7/NOPB requires proper PCB thermal design: the exposed DAP pad must be soldered to a minimum 200 mm² copper pour with ≥4 thermal vias to inner ground planes. With this layout, junction-to-ambient thermal resistance (RθJA) is 32.7°C/W - limiting max ambient temperature to ~85°C at full load to stay within the 125°C max operating junction temperature.
LP3907QSQX-JXI7/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 2.1MHz
- Voltage/Current - Output 1:
- 1.2V, 1A
- Voltage/Current - Output 2:
- 3.3V, 600mA
- Voltage/Current - Output 3:
- 1.8V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-WQFN (4x4)
LP3907QSQX-JXI7/NOPB FAQ
1.How can I place an order for LP3907QSQX-JXI7/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP3907QSQX-JXI7/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP3907QSQX-JXI7/NOPB reliable?
The price and inventory of LP3907QSQX-JXI7/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3907QSQX-JXI7/NOPB is usually 5 days.
3.What payment methods are accepted for LP3907QSQX-JXI7/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3907QSQX-JXI7/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP3907QSQX-JXI7/NOPB?
LP3907QSQX-JXI7/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP3907QSQX-JXI7/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP3907QSQX-JXI7/NOPB?
For technical support, including LP3907QSQX-JXI7/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3907QSQX-JXI7/NOPB requirements.
6.How does Aetrix verify that LP3907QSQX-JXI7/NOPB is sourced from the original manufacturer or authorized distributors?
All LP3907QSQX-JXI7/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3907QSQX-JXI7/NOPB meets industry standards.
7.What is the process for return or replacement of LP3907QSQX-JXI7/NOPB?
All LP3907QSQX-JXI7/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP3907QSQX-JXI7/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP3907QSQX-JXI7/NOPB part is unused and in its original packaging.
Return procedure for LP3907QSQX-JXI7/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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