My Inquiry
My Account
Texas Instruments LP3907SQ-BJXQX/NOPB
- Part No.:
- LP3907SQ-BJXQX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 24-WFQFN Exposed Pad
- Datasheet:
-
LP3907SQ-BJXQX/NOPB.pdf
- Description:
- IC REG QUAD BUCK/LNR SYNC 24WQFN
- Quantity:
- Payment:
- Shipping:
Inventory:4,305
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LP3907SQ-BJXQX/NOPB from Texas Instruments is a programmable power management IC integrating two synchronous buck converters (1 A and 600 mA) and two 300-mA LDOs, all controlled via 400-kHz I²C interface. It operates from 2.8 V to 5.5 V input, delivers 1.2 V/3.3 V default outputs, and features forced PWM mode with disabled UVLO. Used in FPGA core and I/O power sequencing.
For engineers reviewing the LP3907SQ-BJXQX/NOPB datasheet, LP3907SQ-BJXQX/NOPB pinout, LP3907SQ-BJXQX/NOPB application, or LP3907SQ-BJXQX/NOPB equivalent, this device supports dynamic voltage scaling, programmable power-on reset delay, thermal/overcurrent protection, and precision ±3% output regulation - critical for low-power processor and peripheral supply design.
Technical Context
The LP3907SQ-BJXQX/NOPB implements dual synchronous step-down conversion with 2.1-MHz fixed-frequency PWM and automatic PWM-to-PFM transition under light load. Its I²C interface enables independent register-level control of each regulator's enable state, output voltage, sequencing order, and power-good timing.
It integrates two PMOS-based LDOs with 30-mV typical dropout and 45-dB PSRR at 10 kHz, alongside buck converters featuring 1.7–2.1 MHz oscillator, 1.5-A peak current limit on SW1, and 1-A limit on SW2. The device uses internal reference and supports external feedback for precise output adjustment.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.8 V to 5.5 V - supports single-cell Li-ion, USB, or regulated 3.3/5 V rails without external pre-regulation. |
| Buck1 Output | 1.2 V @ 1 A - factory-programmed default for FPGA/DSP core logic supply with ±3% accuracy. |
| Buck2 Output | 3.3 V @ 600 mA - factory-programmed default for I/O or peripheral interface rail. |
| LDO1/LDO2 Output | 2.6 V / 3.3 V @ 300 mA each - programmable range 1 V–3.5 V; used for analog bias, sensor interfaces, or low-noise subsystems. |
| I²C Interface | 400 kHz standard-mode - enables host MCU to configure regulators, monitor status, and manage sequencing without additional GPIOs. |
| UVLO Enable | Disabled - allows operation down to VIN = 2.7 V (per spec), suitable for battery-runoff applications where brownout tolerance is prioritized. |
| Thermal Protection | 160°C shutdown with 20°C hysteresis - prevents permanent damage during sustained overload or poor PCB thermal design. |
Pinout & Package
LP3907SQ-BJXQX/NOPB is packaged in a 24-pin WQFN (RTW) with 4.00 mm × 4.00 mm body and exposed thermal pad (DAP). The package supports high-density layout and efficient heat dissipation when soldered to PCB copper.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1 | Buck1 input power | Accepts 2.8–5.5 V; must be decoupled with ≥10 µF ceramic capacitor near pin. |
| SW1 | Buck1 switch node | Connects to 2.2-µH inductor and output capacitor; requires tight loop layout to minimize EMI. |
| FB1 | Buck1 feedback input | Resistor divider sets output voltage; internal 0.6-V reference enables 1.2-V default via 1:1 ratio. |
| ENSW1 | Buck1 enable control | Logic-high active; can be driven by host or tied high; overrides I²C disable command. |
| VIN2 | Buck2 input power | Independent input path; supports separate source or shared rail with VIN1. |
| SW2 | Buck2 switch node | Drives second inductor-capacitor filter; shares same switching frequency as SW1. |
| FB2 | Buck2 feedback input | Configures 3.3-V output using resistor divider; internal reference ensures stability across temperature. |
| ENSW2 | Buck2 enable control | Independent logic enable; allows staggered startup or fault isolation between rails. |
| VINLDO1 | LDO1 input power | Accepts 1.74–5.5 V; dropout as low as 30 mV enables use after buck stage or low-VIN sources. |
| LDO1 | LDO1 regulated output | Delivers 2.6 V @ 300 mA; low noise (80 µVrms) suits analog/RF subsystems. |
| ENLDO1 | LDO1 enable control | Active-high digital input; synchronized with I²C commands for coordinated power-up. |
| VINLDO2 | LDO2 input power | Separate input pin allows optimization of noise isolation or source selection. |
| LDO2 | LDO2 regulated output | 3.3-V output with same 300-mA capability and 45-dB PSRR for clean I/O supply. |
| ENLDO2 | LDO2 enable control | Enables independent sequencing; supports multi-rail power states like sleep/active modes. |
| SCL/SDA | I²C serial interface | 400-kHz bidirectional bus; requires 4.7-kΩ pull-ups; supports up to 127 devices on shared bus. |
| nPOR | Power-on reset output | Open-drain signal asserting when both Buck1 and Buck2 outputs reach 94% of target; delays configurable via register. |
| EN_T | Sequencing trigger input | External logic pulse initiates full power-on sequence; used for system-level synchronization. |
| GND_SW1/GND_SW2 | Switching ground returns | Separated grounds minimize coupling between buck stages; must connect to common GND plane at DAP. |
| GND_L/GND_C | LDO and core analog grounds | Dedicated ground pins reduce noise injection into sensitive analog blocks and reference circuitry. |
| AVDD/VINLDO12 | Analog supply inputs | Provide clean power to internal reference, I²C logic, and bias circuits; require local 1-µF decoupling. |
| DAP | Thermal pad | Exposed copper pad on underside; must be soldered to PCB thermal plane for RθJA = 32.7°C/W performance. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable Dynamic Voltage Scaling | Host MCU adjusts Buck1/Buck2 output voltages in real time via I²C to match processor workload - reduces dynamic power by up to 40%. |
| Flexible Power-On Sequencing | Configurable startup order and inter-rail delays (0–100 ms) prevent latch-up and ensure safe FPGA configuration before I/O activation. |
| Synchronous Buck Architecture | Integrated high-side/low-side MOSFETs (200 mΩ / 180 mΩ RDS(on)) eliminate external diode losses, enabling >96% peak efficiency at 250 mA. |
| Low-Noise LDO Regulation | 80 µVrms output noise and 45-dB PSRR at 10 kHz support precision ADCs, audio codecs, and RF front-ends without added filtering. |
| Robust Fault Protection | Combined thermal shutdown (160°C), overcurrent limiting (1.5 A Buck1 / 1 A Buck2), and undervoltage lockout prevent damage during abnormal conditions. |
Applications
| FPGA Core Power | DSP I/O Supply |
|---|---|
|
Use Scenario: Powering Xilinx Artix-7 or Intel Cyclone V FPGA core logic requiring tightly regulated 1.2 V at up to 1 A with fast transient response. IC Role / Device Role / Timing Role: LP3907SQ-BJXQX/NOPB Buck1 delivers primary core voltage with programmable soft-start and dynamic scaling during reconfiguration. Use Value: Enables adaptive voltage scaling to reduce FPGA dynamic power by 35% during low-compute intervals while maintaining ±3% regulation. |
Use Scenario: Supplying 3.3 V I/O banks for high-speed parallel interfaces (e.g., DDR2/3, PCIe) with minimal ripple-induced timing jitter. IC Role / Device Role / Timing Role: LP3907SQ-BJXQX/NOPB Buck2 provides stable 3.3 V rail with 96% efficiency and <100 ns load-step response. Use Value: Maintains signal integrity by limiting output ripple to <5 mVpp, preventing setup/hold violations in 200+ MHz data paths. |
| Hearing Aid Audio Subsystem | Portable Test Equipment |
|
Use Scenario: Powering MEMS microphone preamp, low-noise op-amps, and 24-bit sigma-delta ADC in battery-powered hearing aids. IC Role / Device Role / Timing Role: LP3907SQ-BJXQX/NOPB LDO1 (2.6 V) and LDO2 (3.3 V) deliver ultra-low-noise analog supplies with independent enable control. Use Value: 80 µVrms noise and 45-dB PSRR suppress switching artifacts from buck stages, preserving SNR >110 dB in audio chain. |
Use Scenario: Multi-rail power for handheld oscilloscope front-end (1.2 V ADC core, 3.3 V FPGA, 2.6 V sensor interface) operating from Li-ion battery. IC Role / Device Role / Timing Role: LP3907SQ-BJXQX/NOPB integrates all three rails with sequenced startup and battery-runoff capability (UVLO disabled). Use Value: Eliminates need for discrete regulators and sequencing ICs, reducing BOM count by 7 parts and PCB area by 35%. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Triple buck + dual LDO; 2.25–6 V input; no I²C, uses hardware pins for configuration. | Lacks programmable sequencing and DVS; suited for fixed-rail systems without host control. | Choose when firmware control is unnecessary and cost sensitivity outweighs flexibility. |
| LP87332D0RGER | Dual buck + dual LDO; 2.5–5.5 V input; I²C interface; 1.5-A/1.5-A bucks; supports spread-spectrum clocking. | Higher current bucks and advanced EMI reduction; newer process with lower quiescent current (12 µA vs 33 µA). | Prefer for new designs needing higher efficiency, lower noise, or automotive qualification (AEC-Q100). |
Compared with TPS65023RSBR and LP87332D0RGER, the LP3907SQ-BJXQX/NOPB offers unique forced-PWM-only operation and disabled UVLO - making it optimal for battery-runoff scenarios where continuous operation below 2.9 V is required, unlike alternatives that enforce strict input monitoring.
Availability
LP3907SQ-BJXQX/NOPB is available at Aetrix Electronics and suitable for FPGA core power, DSP I/O supply, and portable medical electronics requiring stable component supply with long-term lifecycle assurance.
Supply support for LP3907SQ-BJXQX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, serving industrial, automotive, and communications markets since 1930.
The LP3907 product line targets low-power, multi-rail applications for FPGAs, DSPs, and microprocessors - delivering integrated, I²C-programmable power solutions with minimal external components and robust protection.
FAQ
What is the default output voltage configuration of the LP3907SQ-BJXQX/NOPB?
The LP3907SQ-BJXQX/NOPB is factory-programmed with Buck1 set to 1.2 V (for FPGA core), Buck2 to 3.3 V (for I/O), LDO1 to 2.6 V, and LDO2 to 3.3 V. These defaults are stored in one-time-programmable memory and can be modified via I²C register writes during operation, but retain settings across power cycles only if external EEPROM or host firmware saves them.
Does the LP3907SQ-BJXQX/NOPB support automatic power sequencing without host intervention?
Yes - the LP3907SQ-BJXQX/NOPB includes a dedicated EN_T pin that triggers an internal, register-configurable power-on sequence. When pulsed, it autonomously enables Buck1, Buck2, LDO1, and LDO2 in user-defined order with programmable delays (0–100 ms), eliminating need for external timing components or host CPU involvement during cold start.
How does the disabled UVLO setting affect LP3907SQ-BJXQX/NOPB operation?
The LP3907SQ-BJXQX/NOPB variant has UVLO disabled per Table 3 of the datasheet, allowing operation down to VIN = 2.7 V (below the standard 2.9-V rising threshold). This extends usable battery life in backup or rundown scenarios but requires external supervision if input collapse could damage downstream loads.
Can the LP3907SQ-BJXQX/NOPB operate in PFM mode for light-load efficiency?
No - the LP3907SQ-BJXQX/NOPB is configured for forced PWM mode only (per Table 3), meaning the buck converters maintain constant 2.1-MHz switching regardless of load. This ensures predictable EMI profile and fast transient response but sacrifices some light-load efficiency versus auto-mode variants like LP3907SQ-JXQX/NOPB.
What thermal considerations apply to the LP3907SQ-BJXQX/NOPB in WQFN package?
The LP3907SQ-BJXQX/NOPB in 24-pin WQFN (RTW) has RθJA = 32.7°C/W with proper PCB layout. To sustain 1-A Buck1 operation continuously, the board must provide ≥200 mm² of 2-oz copper connected to the DAP thermal pad. Ambient temperature must be limited to ≤65°C at full load to keep junction temperature below 125°C, per thermal derating guidelines.
LP3907SQ-BJXQX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 2.1MHz
- Voltage/Current - Output 1:
- 1.2V, 1A
- Voltage/Current - Output 2:
- 3.3V, 600mA
- Voltage/Current - Output 3:
- 2.6V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-WQFN (4x4)
LP3907SQ-BJXQX/NOPB FAQ
1.How can I place an order for LP3907SQ-BJXQX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP3907SQ-BJXQX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP3907SQ-BJXQX/NOPB reliable?
The price and inventory of LP3907SQ-BJXQX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3907SQ-BJXQX/NOPB is usually 5 days.
3.What payment methods are accepted for LP3907SQ-BJXQX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3907SQ-BJXQX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP3907SQ-BJXQX/NOPB?
LP3907SQ-BJXQX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP3907SQ-BJXQX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP3907SQ-BJXQX/NOPB?
For technical support, including LP3907SQ-BJXQX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3907SQ-BJXQX/NOPB requirements.
6.How does Aetrix verify that LP3907SQ-BJXQX/NOPB is sourced from the original manufacturer or authorized distributors?
All LP3907SQ-BJXQX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3907SQ-BJXQX/NOPB meets industry standards.
7.What is the process for return or replacement of LP3907SQ-BJXQX/NOPB?
All LP3907SQ-BJXQX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP3907SQ-BJXQX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP3907SQ-BJXQX/NOPB part is unused and in its original packaging.
Return procedure for LP3907SQ-BJXQX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LP3907SQ-BJXQX/NOPB Tags
-
TPS6521905RHBR
Texas Instruments
-
MIC3385YHL-TR
Microchip Technology
-
A4402ELPTR-T
Allegro MicroSystems
-
LM26480SQ-AA/NOPB
Texas Instruments
-
A4402KLPTR-T
Allegro MicroSystems
-
BD71847AMWV-E2
ROHM Semiconductor
-
ADP5040ACPZ-1-R7
Analog Devices Inc.
-
LT3048IDC#TRPBF
Analog Devices Inc.
-
ADP5037ACPZ-R7
Analog Devices Inc.
-
XRP7714ILB-F
MaxLinear, Inc.
-
LTC3260EDE#TRPBF
Analog Devices Inc.
-
LTC3260EMSE#PBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
