Texas Instruments LP3907SQ-VRZX/NOPB
- Part No.:
- LP3907SQ-VRZX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 24-WFQFN Exposed Pad
- Datasheet:
-
LP3907SQ-VRZX/NOPB.pdf
- Description:
- IC REG QUAD BUCK/LNR SYNC 24WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LP3907SQ-VRZX/NOPB from Texas Instruments is a programmable power management IC (PMU) integrating two synchronous buck converters (1 A and 600 mA), two 300-mA LDOs, and a 400-kHz I²C interface - all in a single WQFN-24 package. It delivers precision voltage regulation for FPGA/DSP core and I/O rails, supports dynamic voltage scaling, and features programmable power-on sequencing with external nPOR control.
For engineers reviewing the LP3907SQ-VRZX/NOPB datasheet, LP3907SQ-VRZX/NOPB pinout, LP3907SQ-VRZX/NOPB application, or LP3907SQ-VRZX/NOPB equivalent, this device is selected for low-power embedded systems requiring multi-rail, software-configurable power with thermal and overcurrent protection, high efficiency at light loads (PFM mode), and ±3% output accuracy across temperature.
Technical Context
The LP3907SQ-VRZX/NOPB implements two independent buck regulators with 2.1-MHz PWM switching and automatic PWM-to-PFM transition under light load, enabling >96% peak efficiency and ultra-low quiescent current (33 µA in PFM). Its dual LDOs use PMOS pass devices with 30-mV typical dropout and 45-dB PSRR at 10 kHz, supporting stable analog/IO supplies.
Control is fully I²C-based (400-kHz standard mode), with register-accessible settings for output voltages (Buck1: 0.8–2 V; Buck2: 1–3.5 V; LDOs: 1–3.5 V), enable sequencing, UVLO thresholds (2.7–2.9 V), and power-good delay. Internal reference, thermal shutdown (160°C), and per-rail current limiting ensure robust operation in battery-backed and portable applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.8 V to 5.5 V - supports single-cell Li-ion, USB, or regulated intermediate bus without external pre-regulation. |
| Buck1 Output | 0.8 V–2 V @ 1 A - programmable core voltage for FPGAs/DSPs with ±3% accuracy and 500-µs startup time. |
| Buck2 Output | 1 V–3.5 V @ 600 mA - configurable I/O or peripheral rail with 2.1-MHz switching and PFM mode for <100-µA light-load IQ. |
| LDO1/LDO2 Output | 1 V–3.5 V @ 300 mA each - low-noise (80 µVrms), low-dropout (30 mV typ.) supplies for analog/IO domains. |
| I²C Interface | 400-kHz standard mode - enables host MCU to dynamically adjust voltages, sequence enables, and monitor status registers. |
| Thermal Protection | 160°C shutdown with 20°C hysteresis - prevents permanent damage during sustained overload or poor PCB thermal design. |
| Package | WQFN-24 (4.0 mm × 4.0 mm) - thermally enhanced exposed pad (DAP) for efficient heat dissipation in space-constrained layouts. |
Pinout & Package
LP3907SQ-VRZX/NOPB uses the RTW (WQFN-24) package: 4.0 mm × 4.0 mm body with 0.5-mm pitch and thermally enhanced DAP (exposed ground pad) for improved thermal performance. Pin numbering follows TI's standard top-view layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VINLDO12 | Analog power input | Supplies internal reference, bias, I²C, and logic circuits; must be decoupled with 1-µF ceramic capacitor. |
| EN_T | Power-on sequence enable | Active-high input that initiates preset enable timing for all regulators; used with external RC for delay programming. |
| nPOR | Open-drain power-good output | Asserts low when Buck1/Buck2 outputs fall below 85% of target or rise above 94%; requires 100-kΩ pullup. |
| SW1 / SW2 | Buck switch node outputs | Connect to external inductors (2.2 µH) and output capacitors (10 µF); high-frequency switching nodes demanding tight layout. |
| FB1 / FB2 | Buck feedback inputs | Resistive divider inputs setting output voltage; high-impedance nodes sensitive to noise and trace coupling. |
| LDO1 / LDO2 | LDO regulated outputs | Low-noise, low-dropout outputs for analog/IO; require 0.47–1-µF ceramic output caps with ≤500-mΩ ESR. |
| SDA / SCL | I²C bidirectional data/clock | Standard 400-kHz I²C interface; SDA requires external pullup; both pins support hot-plug and level-shifting. |
| GND_C / GND_L / GND_SW1 / GND_SW2 | Separate ground returns | Isolated analog core (GND_C), LDO (GND_L), and buck power grounds (GND_SW1/SW2) minimize noise coupling between domains. |
Key Features
| Feature | Design Value |
|---|---|
| Dynamic Voltage Scaling (DVS) | Software-adjustable Buck1/Buck2 outputs enable real-time core voltage optimization for performance vs. power trade-offs. |
| PWM-to-PFM Auto Mode Change | Maintains >85% efficiency down to 100-µA load via frequency reduction - critical for battery runtime in standby modes. |
| Programmable Power-On Sequencing | Configurable enable timing (via EN_T + external RC) ensures safe ramp-up order for multi-rail processors and FPGAs. |
| Integrated Power-Good Monitoring | nPOR pin provides synchronized reset assertion for host MCU when either buck output deviates beyond ±6% window. |
| Thermal & Overcurrent Protection | Per-buck current limiting (1.5 A Buck1, 1 A Buck2) and junction shutdown (160°C) prevent fault propagation in compact designs. |
Applications
| FPGA Core & I/O Power | DSP/MCU Multi-Rail Supply |
|---|---|
Use Scenario: Powering Xilinx Spartan or Intel Cyclone FPGA banks with separate core (1.2 V) and I/O (3.3 V) rails. IC Role / Device Role / Timing Role: LP3907SQ-VRZX/NOPB acts as primary PMU, delivering tightly regulated, sequenced, and dynamically scalable voltages via I²C commands from FPGA configuration controller. Use Value: Eliminates discrete DC-DC + LDO combinations; reduces BOM count by 4+ components while enabling voltage margining and adaptive power states. |
Use Scenario: Supplying TI C6000 DSP or ARM Cortex-A series SoCs with core, memory, and peripheral voltages. IC Role / Device Role / Timing Role: LP3907SQ-VRZX/NOPB serves as system-level power hub, coordinating startup timing, monitoring rail health, and adjusting core voltage during DVFS transitions. Use Value: Achieves <100-ms full-system power-up with programmable delays; maintains ±3% output stability across –40°C to +125°C ambient. |
| Portable Medical Electronics | Battery-Backed Industrial Sensors |
Use Scenario: Powering hearing aid ASICs and audio codecs requiring ultra-low noise and precise 1.8-V/2.8-V rails. IC Role / Device Role / Timing Role: LP3907SQ-VRZX/NOPB provides clean LDO outputs (80 µVrms noise) and efficient buck conversion from coin-cell or LiPo sources. Use Value: Enables >100-hour battery life in active mode via PFM efficiency and <0.03-µA shutdown IQ on disabled rails. |
Use Scenario: Maintaining sensor node operation during AC mains failure using supercapacitor or backup battery. IC Role / Device Role / Timing Role: LP3907SQ-VRZX/NOPB manages seamless switchover between primary and backup sources while preserving LDO regulation integrity. Use Value: Undervoltage lockout (2.7 V) and nPOR signaling ensure deterministic reset behavior during brownout events. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Triple buck (2.5 A/1.8 A/1.8 A) + dual LDO (200 mA); no I²C, uses hardware pin strapping for config. | Fixed-output, non-programmable sequencing; suited for cost-sensitive, static-rail applications. | Select when I²C control is unnecessary and higher current per buck is required. |
| MAX8646ETE+ | Dual buck (1.5 A/1.5 A) + triple LDO (300 mA/300 mA/200 mA); I²C interface but no integrated POR or programmable sequencing. | Lacks nPOR output and EN_T sequencing control; requires external reset supervisor for safe startup. | Select when needing three LDOs and higher buck current, accepting added external components for sequencing. |
Compared with TPS65023RSBR and MAX8646ETE+, LP3907SQ-VRZX/NOPB uniquely combines I²C configurability, integrated nPOR, and programmable EN_T sequencing in a compact WQFN-24, making it optimal for FPGA/DSP systems requiring dynamic voltage control and deterministic power-up behavior without external supervisors.
Availability
LP3907SQ-VRZX/NOPB is available at Aetrix Electronics and suitable for FPGA power delivery, portable medical electronics, battery-backed industrial sensors, and DSP-based edge computing platforms requiring stable component supply and long-term lifecycle support.
Supply support for LP3907SQ-VRZX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management solutions, with decades of expertise in high-reliability power IC design.
The LP3907 product line was engineered specifically for low-power, multi-rail applications in FPGAs, DSPs, and portable embedded systems - emphasizing integration, software configurability, and thermal resilience in compact packages.
FAQ
What is the default I²C address for LP3907SQ-VRZX/NOPB?
The LP3907SQ-VRZX/NOPB uses the WQFN-24 (RTW) package, which has a default I²C address of 0x60 (hexadecimal). This address is hardwired and cannot be changed via pins; communication requires proper pullup resistors on SDA and SCL lines per I²C specification.
Does LP3907SQ-VRZX/NOPB support dynamic voltage scaling for both buck converters?
Yes, LP3907SQ-VRZX/NOPB supports independent dynamic voltage scaling for Buck1 and Buck2 via its I²C interface. Registers allow real-time adjustment of output voltages within their respective ranges (Buck1: 0.8–2 V; Buck2: 1–3.5 V), enabling performance/power optimization in FPGA and DSP applications.
What is the minimum input voltage required to operate LP3907SQ-VRZX/NOPB's LDOs?
The LDOs in LP3907SQ-VRZX/NOPB require a minimum input voltage of 1.74 V on their respective VINLDO1 and VINLDO2 pins, as specified in the datasheet. This allows operation from low-voltage sources such as buck converter outputs or partially discharged batteries.
How does the nPOR function work on LP3907SQ-VRZX/NOPB?
The nPOR pin on LP3907SQ-VRZX/NOPB is an open-drain output that goes low when either Buck1 or Buck2 output falls below 85% of its target voltage or rises above 94%. It requires an external 100-kΩ pullup resistor and provides synchronized reset signaling to the host processor during power faults or startup.
Can LP3907SQ-VRZX/NOPB operate in forced PWM mode for both buck converters?
Yes, LP3907SQ-VRZX/NOPB supports forced PWM mode for both Buck1 and Buck2, configurable via I²C register settings. In this mode, switching remains at ~2.1 MHz regardless of load, eliminating frequency variation and associated EMI concerns in noise-sensitive applications.
LP3907SQ-VRZX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 2.1MHz
- Voltage/Current - Output 1:
- 1.8V, 1A
- Voltage/Current - Output 2:
- 2.7V, 600mA
- Voltage/Current - Output 3:
- 3.5V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-WQFN (4x4)
LP3907SQ-VRZX/NOPB FAQ
1.How can I place an order for LP3907SQ-VRZX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP3907SQ-VRZX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP3907SQ-VRZX/NOPB reliable?
The price and inventory of LP3907SQ-VRZX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3907SQ-VRZX/NOPB is usually 5 days.
3.What payment methods are accepted for LP3907SQ-VRZX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3907SQ-VRZX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP3907SQ-VRZX/NOPB?
LP3907SQ-VRZX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP3907SQ-VRZX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP3907SQ-VRZX/NOPB?
For technical support, including LP3907SQ-VRZX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3907SQ-VRZX/NOPB requirements.
6.How does Aetrix verify that LP3907SQ-VRZX/NOPB is sourced from the original manufacturer or authorized distributors?
All LP3907SQ-VRZX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3907SQ-VRZX/NOPB meets industry standards.
7.What is the process for return or replacement of LP3907SQ-VRZX/NOPB?
All LP3907SQ-VRZX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP3907SQ-VRZX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP3907SQ-VRZX/NOPB part is unused and in its original packaging.
Return procedure for LP3907SQ-VRZX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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