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Texas Instruments LP3907SQX-BJXQX/NOPB
- Part No.:
- LP3907SQX-BJXQX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 24-WFQFN Exposed Pad
- Datasheet:
-
LP3907SQX-BJXQX/NOPB.pdf
- Description:
- IC REG QUAD BUCK/LNR SYNC 24WQFN
- Quantity:
- Payment:
- Shipping:
Inventory:3,864
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Product details
Overview
LP3907SQX-BJXQX/NOPB from Texas Instruments is a programmable power management unit (PMU) integrating two synchronous buck converters (1 A and 600 mA), two 300-mA LDOs, and a 400-kHz I²C interface. It delivers 1.2 V/1 A (Buck1), 3.3 V/600 mA (Buck2), 2.6 V/300 mA (LDO1), and 3.3 V/300 mA (LDO2) for FPGA core and I/O rail sequencing in battery-powered portable electronics.
For engineers reviewing the LP3907SQX-BJXQX/NOPB datasheet, LP3907SQX-BJXQX/NOPB pinout, LP3907SQX-BJXQX/NOPB application, or LP3907SQX-BJXQX/NOPB equivalent, this device supports dynamic voltage scaling, programmable power-on sequencing, thermal/overcurrent protection, and flexible POR delay-critical for low-power embedded systems with strict supply-rail coordination requirements.
Technical Context
The LP3907SQX-BJXQX/NOPB implements dual synchronous step-down conversion using internal PMOS/NMOS FETs (RDSON_P = 200 mΩ, RDSON_N = 180 mΩ) with forced PWM mode and 2.1-MHz fixed-frequency operation. Its I²C interface enables real-time register access to configure output voltages, enable states, sequencing delays, and UVLO thresholds.
Each LDO uses a PMOS pass device with 30-mV typical dropout at 50 mA and supports 1–3.5 V programmable outputs (excluding JJ11/FX6W/JX6X variants); LP3907SQX-BJXQX/NOPB is factory-configured for 2.6 V on LDO1 and 3.3 V on LDO2, with EN_T disabled per Table 3.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.8 V to 5.5 V - supports single-cell Li-ion, USB, or regulated intermediate rails without external pre-regulation. |
| Buck1 Output | 1.2 V @ 1 A - factory-programmed for FPGA core logic supply with ±3% accuracy and automatic soft-start. |
| Buck2 Output | 3.3 V @ 600 mA - factory-programmed for peripheral I/O with 96% peak efficiency and PWM-to-PFM light-load mode. |
| LDO1/LDO2 Outputs | 2.6 V / 3.3 V @ 300 mA each - low-noise (80 µVrms), low-dropout (30 mV typ.) supplies for analog/RF subsystems. |
| I²C Interface | 400 kHz standard-mode - enables host processor to dynamically adjust voltages, sequence timing, and monitor status registers. |
| Thermal Protection | 160°C shutdown with 20°C hysteresis - prevents permanent damage during sustained overload or poor PCB thermal design. |
| UVLO Threshold | 2.7 V (falling), 2.9 V (rising) - disables all regulators below safe input voltage to prevent brownout instability. |
Pinout & Package
LP3907SQX-BJXQX/NOPB is packaged in a 24-pin WQFN (RTW) with 4.00 mm × 4.00 mm body and exposed thermal pad (DAP). The package supports high-density layout and efficient heat dissipation via PCB copper pour under the DAP.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| VINLDO12 | Analog power input | Supplies internal reference, bias, I²C, and logic circuits; must be decoupled with 1 µF ceramic capacitor. |
| EN_T | Power-on sequence enable | Logic input that initiates factory-programmed sequencing; LP3907SQX-BJXQX/NOPB has EN_T disabled per Table 3. |
| nPOR | Open-drain power-good output | Signals valid Buck1/Buck2 output (94% rising, 85% falling threshold); requires external 100-kΩ pullup. |
| GND_SW1 / GND_SW2 | Switching ground returns | Separate low-impedance paths for Buck1/Buck2 NMOS sources to minimize noise coupling into analog sections. |
| SW1 / SW2 | Switch node outputs | Connect to external 2.2-µH inductors and 10-µF output capacitors; high dv/dt nodes requiring tight loop layout. |
| FB1 / FB2 | Feedback inputs | Resistive divider inputs for precise output voltage regulation; high-impedance nodes sensitive to leakage. |
| VIN1 / VIN2 | Buck input supplies | Independent inputs allow separate sourcing (e.g., battery + DC/DC) for Buck1 and Buck2 with distinct UVLO monitoring. |
| LDO1 / LDO2 | Linear regulator outputs | Low-noise, low-ESR outputs requiring ≥0.47 µF ceramic capacitors with ≤500 mΩ ESR for stability. |
| ENLDO1 / ENLDO2 | LDO enable inputs | Active-high digital controls enabling independent LDO power gating for system-level power state management. |
| SDA / SCL | I²C bidirectional data/clock | 400-kHz interface compliant with standard-mode I²C; requires external pullups per bus capacitance constraints. |
Key Features
| Feature | Design Value |
|---|---|
| Dynamic voltage scaling (DVS) | Real-time I²C control of Buck1/Buck2 output voltages enables adaptive power management for variable workload processors. |
| Programmable power-on sequencing | Configurable delay between Buck1, Buck2, LDO1, and LDO2 startup prevents backfeeding and ensures proper system initialization. |
| Synchronous rectification | Integrated NMOS switches eliminate external diodes, reducing conduction loss and improving light-load efficiency over 96% peak. |
| Flexible POR with delay function | nPOR asserts only after all enabled rails stabilize within ±6% of target, with user-selectable delay to coordinate downstream logic reset timing. |
| Thermal and current protection | Automatic shutdown at 160°C junction temperature and cycle-by-cycle peak current limiting (1.5 A Buck1, 1 A Buck2) ensure robust operation. |
Applications
| FPGA Core Power | Peripheral I/O Power |
|---|---|
|
Use Scenario: Powering Xilinx Spartan-7 or Intel MAX 10 FPGA core logic operating at 1.2 V with dynamic load currents up to 1 A. IC Role / Device Role / Timing Role: LP3907SQX-BJXQX/NOPB provides tightly regulated 1.2 V core supply with soft-start and DVS support for low-power modes. Use Value: Enables reliable FPGA configuration and operation across temperature (-40°C to +125°C) with ±3% output accuracy and <500 µs startup time. |
Use Scenario: Supplying 3.3 V I/O banks for memory interfaces (SPI, QSPI), sensors, and communication peripherals in handheld medical devices. IC Role / Device Role / Timing Role: LP3907SQX-BJXQX/NOPB delivers clean, low-noise 3.3 V from a shared 3.6–5.5 V input rail with independent enable control. Use Value: Reduces board area by consolidating two buck and two LDO supplies into one IC, while maintaining PSRR >45 dB at 10 kHz for signal integrity. |
| Hearing Aid DSP Power | Electronic Measurement Unit |
|
Use Scenario: Powering ultra-low-power DSPs (e.g., TI C55xx) in Class B hearing aids requiring sub-100 µA quiescent current in standby. IC Role / Device Role / Timing Role: LP3907SQX-BJXQX/NOPB operates Buck2 in PFM mode at light loads and shuts down unused blocks via I²C to minimize system idle current. Use Value: Achieves <33 µA quiescent current in PFM mode and 0.01 µA shutdown current, extending battery life in coin-cell-powered devices. |
Use Scenario: Providing precision analog and digital supplies for handheld multimeters with isolated ADC front-ends and LCD drivers. IC Role / Device Role / Timing Role: LP3907SQX-BJXQX/NOPB separates noisy switching grounds (GND_SW1/GND_SW2) from analog ground (GND_C) to preserve measurement accuracy. Use Value: Delivers 2.6 V LDO1 with 80 µVrms output noise and <0.15%/V line regulation, minimizing offset drift in 4½-digit measurement circuits. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Triple buck (1.5 A/1 A/1 A) + dual LDO (250 mA), 2.7–5.5 V input, no DVS, fixed 2.25-MHz switching | Higher current capability but lacks I²C programmability and flexible sequencing; suited for fixed-voltage industrial controllers | Select when fixed outputs and higher current outweigh need for dynamic voltage scaling and fine-grained sequencing control. |
| MAX8646ETE+ | Dual buck (1.5 A/1.5 A) + triple LDO (300 mA), 2.5–5.5 V input, 1.1–3.3 V programmable outputs, 2.2-MHz switching | Includes third LDO and higher buck current, but uses SMBus (not I²C) and lacks nPOR with delay function | Prefer when three independent LDOs are required and SMBus compatibility exists in host system architecture. |
Compared with TPS65023RSBR and MAX8646ETE+, LP3907SQX-BJXQX/NOPB uniquely combines I²C-based DVS, factory-configurable sequencing (including EN_T disable), and integrated nPOR with delay-making it optimal for portable FPGA/DSP platforms demanding coordinated, adaptive power delivery.
Availability
LP3907SQX-BJXQX/NOPB is available at Aetrix Electronics and suitable for FPGA core power, peripheral I/O power, hearing aid DSP power, electronic measurement units, and equipment run-off of battery backup requiring stable component supply across industrial and medical product lifecycles.
Supply support for LP3907SQX-BJXQX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability power solutions for aerospace, industrial, and medical applications.
LP3907SQX-BJXQX/NOPB belongs to TI's low-power PMU product line, designed specifically for space-constrained, battery-operated portable electronics requiring precise multi-rail sequencing, dynamic voltage scaling, and robust protection features.
FAQ
What is the default output voltage configuration of LP3907SQX-BJXQX/NOPB?
The LP3907SQX-BJXQX/NOPB is factory-programmed with Buck1 set to 1.2 V (1 A), Buck2 to 3.3 V (600 mA), LDO1 to 2.6 V (300 mA), and LDO2 to 3.3 V (300 mA), as specified in Table 3 of the SNVS511U datasheet. These values are stored in nonvolatile memory and persist across power cycles without host I²C intervention.
Does LP3907SQX-BJXQX/NOPB support dynamic voltage scaling (DVS) for both buck converters?
Yes, LP3907SQX-BJXQX/NOPB supports full I²C-based DVS for both Buck1 and Buck2. The device allows real-time adjustment of output voltages within their respective ranges (Buck1: 0.8–2.0 V; Buck2: 1.0–3.5 V) via register writes, enabling adaptive power management for processors with variable performance states.
What is the purpose of the EN_T pin on LP3907SQX-BJXQX/NOPB, and is it active by default?
The EN_T pin initiates the factory-programmed power-on sequencing sequence. For LP3907SQX-BJXQX/NOPB, EN_T is disabled per Table 3 (DEFAULT EN_T = 010, DEFAULT UVLO = Disabled), meaning sequencing is controlled solely by individual enable pins (ENSW1, ENSW2, ENLDO1, ENLDO2) rather than a global trigger.
How does the nPOR function operate on LP3907SQX-BJXQX/NOPB, and what are its thresholds?
The nPOR pin on LP3907SQX-BJXQX/NOPB is an open-drain output signaling valid operation of Buck1 and Buck2. It asserts low when either output falls below 85% of target or rises above 94% of target during startup. A 100-kΩ external pullup is required, and the pin remains active until both rails stabilize within specification.
What package type and thermal characteristics apply to LP3907SQX-BJXQX/NOPB?
LP3907SQX-BJXQX/NOPB uses the 24-pin WQFN (RTW) package with 4.00 mm × 4.00 mm footprint and exposed thermal pad. Its junction-to-ambient thermal resistance (RθJA) is 32.7°C/W, and junction-to-board (RθJB) is 11.2°C/W-requiring adequate PCB copper area under the DAP for reliable operation at full load in 85°C ambient.
LP3907SQX-BJXQX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 2.1MHz
- Voltage/Current - Output 1:
- 1.2V, 1A
- Voltage/Current - Output 2:
- 3.3V, 600mA
- Voltage/Current - Output 3:
- 2.6V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-WQFN (4x4)
LP3907SQX-BJXQX/NOPB FAQ
1.How can I place an order for LP3907SQX-BJXQX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP3907SQX-BJXQX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP3907SQX-BJXQX/NOPB reliable?
The price and inventory of LP3907SQX-BJXQX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3907SQX-BJXQX/NOPB is usually 5 days.
3.What payment methods are accepted for LP3907SQX-BJXQX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3907SQX-BJXQX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP3907SQX-BJXQX/NOPB?
LP3907SQX-BJXQX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP3907SQX-BJXQX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP3907SQX-BJXQX/NOPB?
For technical support, including LP3907SQX-BJXQX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3907SQX-BJXQX/NOPB requirements.
6.How does Aetrix verify that LP3907SQX-BJXQX/NOPB is sourced from the original manufacturer or authorized distributors?
All LP3907SQX-BJXQX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3907SQX-BJXQX/NOPB meets industry standards.
7.What is the process for return or replacement of LP3907SQX-BJXQX/NOPB?
All LP3907SQX-BJXQX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP3907SQX-BJXQX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP3907SQX-BJXQX/NOPB part is unused and in its original packaging.
Return procedure for LP3907SQX-BJXQX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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