Texas Instruments LP3907SQX-PFX6W/NOPB
- Part No.:
- LP3907SQX-PFX6W/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 24-WFQFN Exposed Pad
- Datasheet:
-
LP3907SQX-PFX6W/NOPB.pdf
- Description:
- IC REG QUAD BUCK/LNR SYNC 24WQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LP3907SQX-PFX6W/NOPB from Texas Instruments is a programmable power management IC integrating two synchronous buck converters (1 A and 600 mA) and two 300-mA LDOs, all controlled via 400-kHz I²C interface. It operates from 2.8 V to 5.5 V input, delivers 1 V/3.3 V buck outputs and 2.65 V/3.2 V LDO outputs in Forced PWM mode, and supports dynamic voltage scaling for FPGA core and I/O rails.
For engineers reviewing the LP3907SQX-PFX6W/NOPB datasheet, LP3907SQX-PFX6W/NOPB pinout, LP3907SQX-PFX6W/NOPB application, or LP3907SQX-PFX6W/NOPB equivalent, this device is selected for multi-rail battery-powered systems requiring precise sequencing, light-load efficiency, and host-controlled regulation - especially where thermal performance in WQFN-24 and I²C register accessibility are critical design factors.
Technical Context
The LP3907SQX-PFX6W/NOPB implements dual synchronous step-down conversion with 2.1-MHz fixed-frequency PWM and automatic PWM-to-PFM transition under light load, plus two PMOS-based LDOs with 30-mV typical dropout. Its I²C interface enables real-time readback of status registers and full configuration of output voltages, enable timing, and power-on reset delay.
It features integrated power-on reset with programmable delay (010 = 100 ms), undervoltage lockout (2.7 V–2.9 V), thermal shutdown (160 °C), and overcurrent protection on both bucks and LDOs. The device uses separate analog (AVDD, VINLDO12) and core (VIN1, VIN2, VINLDO1, VINLDO2) supply domains to minimize noise coupling between switching and linear regulators.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.8 V to 5.5 V - supports single-cell Li-ion, USB, and wide-input industrial supplies without external pre-regulation. |
| Buck1 Output | 1 V at 1 A - factory-programmed for low-voltage FPGA/DSP core rail with ±3% accuracy and 2.1-MHz switching. |
| Buck2 Output | 3.3 V at 600 mA - fixed for peripheral I/O or interface logic, enabling high-efficiency conversion from 5-V sources. |
| LDO1 Output | 2.65 V at 300 mA - PMOS-based with 30-mV dropout, suitable for noise-sensitive analog or reference circuits. |
| LDO2 Output | 3.2 V at 300 mA - independently programmable, optimized for mixed-signal subsystems requiring clean biasing. |
| I²C Interface | 400-kHz standard-mode - allows host MCU to configure outputs, monitor faults (nPOR), and manage sequencing without additional GPIOs. |
| Package | 24-pin WQFN (RTW), 4.0 mm × 4.0 mm - thermally enhanced with exposed DAP for PCB heat sinking in space-constrained designs. |
Pinout & Package
LP3907SQX-PFX6W/NOPB is housed in a 24-pin WQFN (RTW) package with 0.5-mm pitch and thermally enhanced exposed die attach pad (DAP). The DAP must be soldered to a thermal pad on the PCB for optimal junction-to-board thermal resistance (RθJB = 11.2 °C/W).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1 | Buck1 input power | Accepts 2.8–5.5 V; minimum input for 1-V output is 2.0 V (VOUT + 1 V). |
| SW1 | Buck1 switch node | Connects to external 2.2-µH inductor and 10-µF output capacitor; requires low-ESR ceramic layout. |
| FB1 | Buck1 feedback input | Resistor-divider input setting 1-V output; internal 0.6-V reference enables precision regulation. |
| ENSW1 | Buck1 enable control | Active-high digital input; overrides I²C control when asserted externally. |
| VINLDO1 | LDO1 input power | Supplies LDO1; supports down to 1.74 V input, enabling cascaded regulation from buck outputs. |
| LDO1 | LDO1 regulated output | Delivers 2.65 V at up to 300 mA with 30-mV dropout and 45-dB PSRR at 10 kHz. |
| ENLDO1 | LDO1 enable control | Active-high logic input; independent of I²C, allowing hardware-level sequencing. |
| SCL / SDA | I²C clock/data | 400-kHz bidirectional interface; requires 10-kΩ pull-ups to AVDD for proper bus operation. |
| nPOR | Power-on reset output | Open-drain signal asserting low until both Buck1 and Buck2 reach ≥94% of target voltage. |
| DAP | Thermal ground | Exposed pad tied to PCB ground plane; mandatory for thermal reliability above 0.5 W dissipation. |
Key Features
| Feature | Design Value |
|---|---|
| Forced PWM Mode | Eliminates frequency variation and audible noise in buck regulators - essential for EMI-sensitive medical and audio applications. |
| Programmable Power-On Reset Delay | 010 code sets 100-ms nPOR assertion delay, enabling safe sequencing of downstream FPGAs before release. |
| Separate Analog & Core Power Domains | VINLDO12 and AVDD isolate I²C, reference, and bias circuitry from noisy switcher grounds, improving ADC/SAR converter SNR. |
| Thermal & Overcurrent Protection | Auto-shutdown at 160 °C with 20 °C hysteresis and cycle-by-cycle current limiting prevent damage during transient overload or poor heatsinking. |
| Low Quiescent Current | 33 µA in PFM no-load mode and 0.01 µA shutdown current extend battery life in always-on hearing aid and sensor nodes. |
Applications
| FPGA Core Power | DSP I/O Supply |
|---|---|
Use Scenario: Powering Xilinx Spartan-7 or Intel MAX 10 FPGA core logic operating at 1 V with dynamic voltage scaling. IC Role / Device Role / Timing Role: LP3907SQX-PFX6W/NOPB delivers tightly regulated 1-V core rail with I²C-adjustable voltage and soft-start to prevent inrush. Use Value: Enables adaptive power management during FPGA configuration and runtime reconfiguration, reducing average system power by >25%. |
Use Scenario: Supplying 3.3-V I/O banks for TI C674x DSPs interfacing with external memory and peripherals. IC Role / Device Role / Timing Role: LP3907SQX-PFX6W/NOPB provides low-noise, high-PSSR 3.3-V rail synchronized to processor boot sequence via nPOR. Use Value: Eliminates need for discrete LDO post-regulation, saving board area while maintaining <10-mV ripple under 500-mA load transients. |
| Hearing Aid Front-End | Electronic Measurement Unit |
Use Scenario: Dual-rail power for ultra-low-power MEMS microphone preamp (2.65 V) and ADC driver (3.2 V) in Class-D hearing aids. IC Role / Device Role / Timing Role: LP3907SQX-PFX6W/NOPB supplies clean, sequenced analog rails with <80-µVrms output noise and <300-µs startup. Use Value: Meets EN 50106 hearing aid immunity requirements by minimizing conducted noise coupling into sensitive audio paths. |
Use Scenario: Powering handheld multimeters with isolated analog front-end (2.65 V) and digital controller (3.3 V) from single Li-ion cell. IC Role / Device Role / Timing Role: LP3907SQX-PFX6W/NOPB manages brownout-safe sequencing and monitors UVLO to trigger graceful shutdown before battery depletion. Use Value: Extends usable battery capacity by 18% versus fixed-output PMICs through adaptive buck/LDO load matching. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail PMU applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Triple buck (2.5/1.8/1.2 V) + dual LDO (1.8/3.3 V); no I²C, only hardware pin-strapping. | Lacks dynamic voltage scaling and real-time telemetry; suited for fixed-function embedded controllers. | Select when I²C overhead is unacceptable and output voltages are static across product lifecycle. |
| MAX20029ATGB/V+T | Dual buck (3.3/1.2 V) + dual LDO (3.3/1.2 V); 2.2-MHz sync, but no programmable POR delay or nPOR open-drain output. | Requires external reset supervisor for FPGA sequencing; lower max input (4.5 V) limits single-cell Li-ion headroom. | Choose for automotive AEC-Q100 Grade 2 compliance where extended temperature range (−40°C to +125°C) is mandatory. |
Compared with TPS65023RSBR and MAX20029ATGB/V+T, LP3907SQX-PFX6W/NOPB uniquely combines I²C configurability, programmable POR delay, and PMOS LDOs in a thermally optimized WQFN - making it the preferred choice for portable, software-defined power systems requiring field-upgradable voltage policies.
Availability
LP3907SQX-PFX6W/NOPB is available at Aetrix Electronics and suitable for FPGA core power, DSP I/O supply, hearing aid front-end, electronic measurement units, and battery-backed equipment requiring stable component supply across long production lifecycles.
Supply support for LP3907SQX-PFX6W/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and power management solutions with deep expertise in low-power system design and high-reliability manufacturing.
The LP3907 product line targets portable and battery-operated devices requiring compact, intelligent power management - specifically engineered for FPGAs, DSPs, and mixed-signal SoCs needing dynamic voltage scaling, precise sequencing, and minimal quiescent current.
FAQ
What is the default I²C address for LP3907SQX-PFX6W/NOPB?
The LP3907SQX-PFX6W/NOPB uses the 24-pin WQFN (RTW) package, which has a default I²C address of 0x60 (hexadecimal). This address is hardwired and cannot be changed via pins or registers. The device supports standard-mode (100 kHz) and fast-mode (400 kHz) I²C communication, and the SCL/SDA lines require external 10-kΩ pull-up resistors to AVDD for reliable bus operation. Always verify address collision in multi-device systems before firmware integration.
Does LP3907SQX-PFX6W/NOPB support dynamic voltage scaling (DVS)?
Yes, LP3907SQX-PFX6W/NOPB supports dynamic voltage scaling via its I²C interface: Buck1 and Buck2 output voltages can be reprogrammed in-circuit across their full ranges (Buck1: 0.8–2.0 V; Buck2: 1.0–3.5 V). This capability is used during FPGA partial reconfiguration or DSP workload adaptation. The LP3907SQX-PFX6W/NOPB implements automatic soft-start on each voltage change to limit inrush current and maintain system stability without external intervention.
What is the thermal performance of LP3907SQX-PFX6W/NOPB in its WQFN package?
LP3907SQX-PFX6W/NOPB in the 24-pin WQFN (RTW) package has a junction-to-ambient thermal resistance (RθJA) of 32.7 °C/W and junction-to-board (RθJB) of 11.2 °C/W when mounted per TI layout guidelines. With the DAP soldered to a 400-mm² copper thermal pad, it sustains 1.43 W maximum power dissipation at 85 °C ambient. Thermal shutdown activates at 160 °C (typical) with 20 °C hysteresis, ensuring robust operation in sealed enclosures or high-temperature industrial environments.
Can LP3907SQX-PFX6W/NOPB operate with input voltages below 2.8 V?
No - LP3907SQX-PFX6W/NOPB has a specified minimum input voltage of 2.8 V for all power blocks (buck and LDO inputs) per Recommended Operating Conditions. However, the LDO input pins (VINLDO1, VINLDO2) are rated down to 1.74 V, enabling use as post-regulators fed from a higher-voltage buck output. For example, if Buck1 delivers 3.3 V, that rail may directly supply VINLDO1 to generate 2.65 V, even when main input drops to 2.8 V. Direct sub-2.8-V main supply violates absolute maximum ratings and risks functional failure.
How does the nPOR function work on LP3907SQX-PFX6W/NOPB?
The nPOR pin on LP3907SQX-PFX6W/NOPB is an open-drain output that remains low until both Buck1 and Buck2 outputs reach ≥94% of their target voltages and stay within regulation for the programmed delay period (010 = 100 ms for LP3907SQX-PFX6W/NOPB). It asserts low again if either output falls below 85% of target. This signal drives FPGA/ASIC reset inputs directly, eliminating need for external supervisors. A 100-kΩ internal pull-up ensures defined logic level when inactive.
LP3907SQX-PFX6W/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 2.1MHz
- Voltage/Current - Output 1:
- 1V, 1A
- Voltage/Current - Output 2:
- 3.3V, 600mA
- Voltage/Current - Output 3:
- 2.65V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-WQFN (4x4)
LP3907SQX-PFX6W/NOPB FAQ
1.How can I place an order for LP3907SQX-PFX6W/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP3907SQX-PFX6W/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP3907SQX-PFX6W/NOPB reliable?
The price and inventory of LP3907SQX-PFX6W/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3907SQX-PFX6W/NOPB is usually 5 days.
3.What payment methods are accepted for LP3907SQX-PFX6W/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3907SQX-PFX6W/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP3907SQX-PFX6W/NOPB?
LP3907SQX-PFX6W/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP3907SQX-PFX6W/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP3907SQX-PFX6W/NOPB?
For technical support, including LP3907SQX-PFX6W/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3907SQX-PFX6W/NOPB requirements.
6.How does Aetrix verify that LP3907SQX-PFX6W/NOPB is sourced from the original manufacturer or authorized distributors?
All LP3907SQX-PFX6W/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3907SQX-PFX6W/NOPB meets industry standards.
7.What is the process for return or replacement of LP3907SQX-PFX6W/NOPB?
All LP3907SQX-PFX6W/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP3907SQX-PFX6W/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP3907SQX-PFX6W/NOPB part is unused and in its original packaging.
Return procedure for LP3907SQX-PFX6W/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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