Texas Instruments LP3907SQX-VRZX/NOPB
- Part No.:
- LP3907SQX-VRZX/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 24-WFQFN Exposed Pad
- Datasheet:
-
LP3907SQX-VRZX/NOPB.pdf
- Description:
- IC REG QUAD BUCK/LNR SYNC 24WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:4,500
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Product details
Overview
LP3907SQX-VRZX/NOPB from Texas Instruments is a programmable power management IC integrating two synchronous buck converters (1 A and 600 mA) and two 300-mA LDOs, all controlled via 400-kHz I²C interface. It operates from 2.8 V to 5.5 V input, delivers ±3% output voltage accuracy, and supports dynamic voltage scaling for FPGA/DSP core and I/O rails in portable medical and industrial embedded systems.
For engineers reviewing the LP3907SQX-VRZX/NOPB datasheet, LP3907SQX-VRZX/NOPB pinout, LP3907SQX-VRZX/NOPB application, or LP3907SQX-VRZX/NOPB equivalent, this device offers verified I²C-programmable regulation, thermal/overcurrent protection, automatic PWM-to-PFM mode transition, and flexible power-on sequencing - critical for low-power processor subsystems requiring precise rail coordination and battery-aware efficiency.
Technical Context
The LP3907SQX-VRZX/NOPB implements dual independent buck regulators with 2.1-MHz fixed-frequency PWM operation and seamless transition to PFM at light loads, maintaining >90% efficiency down to 1 mA. Each buck includes internal high-side/low-side MOSFETs (RDSON_P = 200 mΩ, RDSON_N = 180 mΩ), soft-start, and dedicated feedback (FB1/FB2) with ±3% regulation tolerance.
Its dual LDOs feature PMOS pass devices with 30-mV typical dropout at 50 mA, 45-dB PSRR at 10 kHz, and 80-µVrms output noise. All regulators are individually enabled via dedicated digital inputs (ENSW1/ENSW2/ENLDO1/ENLDO2), while nPOR provides synchronized power-good signaling for both bucks with 50-ms default delay.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Input Voltage Range | 2.8 V to 5.5 V - supports single-cell Li-ion, USB, or regulated 3.3-V/5-V rails without external pre-regulation |
| Buck1 Output | 0.8 V–2.0 V @ 1 A - programmable core voltage for FPGA/DSP logic domains with ±3% accuracy |
| Buck2 Output | 1.0 V–3.5 V @ 600 mA - configurable I/O or peripheral supply with automatic light-load PFM mode |
| LDO1/LDO2 Output | 1.0 V–3.5 V @ 300 mA each - low-noise, low-dropout supplies for analog/RF sections or memory interfaces |
| I²C Interface | 400-kHz standard-mode - enables host MCU to dynamically adjust voltages, sequence enables, and monitor status registers |
| Thermal Protection | 160°C shutdown with 20°C hysteresis - prevents permanent damage during sustained overload or poor PCB thermal design |
| Power-On Reset | nPOR open-drain output with 50-ms default delay - asserts reset until both buck outputs stabilize within 94% of target |
Pinout & Package
LP3907SQX-VRZX/NOPB uses the 24-pin WQFN (RTW) package, 4.00 mm × 4.00 mm, with exposed thermal pad (DAP) recommended for soldering to improve thermal dissipation. Pin numbering follows top-view layout with GND connections distributed across pins 4, 9, 15, 18, and DAP.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VIN1, VIN2, VINLDO1, VINLDO2 | Independent input power rails | Enables multi-source power architecture - e.g., VIN1 from battery, VIN2 from USB, LDO inputs from buck outputs |
| SW1, SW2 | Buck switch node outputs | Drive external 2.2-µH inductors; require low-ESR ceramic output capacitors (10 µF each) for stability |
| FB1, FB2 | Resistive feedback inputs | Set buck output voltage via external resistor dividers; internal reference = 0.6 V (typical) |
| LDO1, LDO2 | Regulated linear outputs | Deliver low-noise, fast-transient power; require ≥0.47 µF ceramic output capacitance per LDO |
| ENSW1, ENSW2, ENLDO1, ENLDO2 | Digital enable inputs | Active-high logic control allows precise power-up/down sequencing under host MCU or state-machine supervision |
| SDA, SCL | I²C bidirectional data/clock | Supports standard-mode 400-kHz communication; requires 10-kΩ pull-ups to AVDD (pin 10) |
| nPOR | Open-drain power-good indicator | Sinks current when either buck output falls below 85% of target; used to hold system in reset until stable |
| DAP | Exposed thermal pad | Not electrically connected; must be soldered to PCB ground plane to achieve RθJA = 32.7°C/W |
Key Features
| Feature | Design Value |
|---|---|
| Dynamic Voltage Scaling (DVS) | I²C-programmable buck output adjustment enables real-time core voltage tuning for performance vs. power trade-offs in FPGAs |
| PWM-to-PFM Automatic Mode Change | Maintains >85% efficiency at 100-µA load by reducing switching frequency and quiescent current to 33 µA in PFM mode |
| Programmable Power-On Sequencing | Configurable enable timing via I²C registers ensures safe ramp-up order - e.g., LDOs before bucks, or core before I/O |
| Integrated Precision Reference | 0.6-V internal bandgap reference with <±1% drift over −40°C to +125°C enables accurate closed-loop regulation without external components |
| Undervoltage Lockout (UVLO) | 2.7 V (falling) / 2.9 V (rising) threshold on VINLDO12 prevents erratic operation during brownout conditions |
| Thermal & Overcurrent Protection | Hardware-level shutdown at 160°C junction temperature and 1.5-A (Buck1)/1-A (Buck2) peak current limit prevent fault propagation |
Applications
| FPGA Core & I/O Power | Portable Medical Instrumentation |
|---|---|
Use Scenario: Powering Xilinx Spartan-7 FPGA with separate 1.2-V core and 3.3-V I/O banks from a single 3.6-V Li-ion cell. IC Role / Device Role / Timing Role: LP3907SQX-VRZX/NOPB delivers sequenced, I²C-adjustable rails with nPOR coordination to meet FPGA configuration timing requirements. Use Value: Eliminates discrete DC-DC + LDO combinations; reduces BOM count by 6 components while enabling dynamic core voltage scaling during low-power modes. |
Use Scenario: Supplying analog front-end (AFE), microcontroller, and display backlight in a handheld hearing aid analyzer. IC Role / Device Role / Timing Role: LP3907SQX-VRZX/NOPB provides ultra-low-noise LDO outputs for AFE biasing and efficient bucks for digital logic, all synchronized via I²C. Use Value: Achieves 80-µVrms LDO noise and <100-µA quiescent current in shutdown - extending battery life beyond 12 hours per charge. |
| Industrial Sensor Node | Electronic Measurement Unit |
Use Scenario: Powering ARM Cortex-M4 MCU, RS-485 transceiver, and MEMS accelerometer in a battery-operated condition monitoring sensor. IC Role / Device Role / Timing Role: LP3907SQX-VRZX/NOPB manages three independent rails (1.8-V MCU, 3.3-V interface, 2.5-V sensor) with programmable enable delays. Use Value: Enables firmware-controlled power gating of peripherals; reduces system standby current to 3 µA via VINLDO12 shutdown mode. |
Use Scenario: Regulating precision ADC reference, op-amp supplies, and microcontroller in a handheld multimeter with auto-ranging capability. IC Role / Device Role / Timing Role: LP3907SQX-VRZX/NOPB supplies clean 2.5-V LDO rail for ADC reference and 3.3-V buck for digital logic with <±0.01% line regulation. Use Value: Delivers 45-dB PSRR at 10 kHz and ±3% output accuracy - meeting Class II metering accuracy standards without external filtering. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Triple buck (2×1.5 A, 1×1 A) + dual LDO (2×200 mA); no I²C, uses hardware pin-strapping for configuration | Fixed-output variant; lacks dynamic voltage scaling and programmable sequencing - suitable only for static rail assignments | Select when I²C control is unnecessary and higher buck current is required for SoC applications |
| LP87332D0RGER | Dual buck (2×1.5 A) + dual LDO (2×300 mA); I²C interface with enhanced register set and integrated watchdog timer | Includes hardware reset supervisor and fault logging; supports tighter voltage tolerances (±1.5%) and lower quiescent current (12 µA) | Prefer for safety-critical systems requiring diagnostic capability and extended battery runtime |
Compared with TPS65023RSBR and LP87332D0RGER, LP3907SQX-VRZX/NOPB offers balanced integration of I²C programmability, thermal robustness, and cost-effective dual-buck/dual-LDO topology - making it optimal for mid-tier portable electronics where flexibility and proven reliability outweigh need for advanced diagnostics or ultra-low IQ.
Availability
LP3907SQX-VRZX/NOPB is available at Aetrix Electronics and suitable for FPGA power, portable medical instrumentation, industrial sensor nodes, electronic measurement units, and battery-backed equipment requiring stable component supply and long-term production support.
Supply support for LP3907SQX-VRZX/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with decades of expertise in power management IC design for high-reliability applications.
The LP3907 product line targets low-power, multi-rail systems such as FPGAs, DSPs, and portable medical devices - delivering integrated buck/LDO regulation with I²C configurability and robust protection features in compact WQFN packages.
FAQ
What is the default I²C address for LP3907SQX-VRZX/NOPB?
The LP3907SQX-VRZX/NOPB uses the 24-pin WQFN (RTW) package, which has a default I²C address of 0x60 (hexadecimal). This address is hardwired and cannot be changed via pins or registers. Communication occurs at 400-kHz standard-mode speed, and the device supports repeated start conditions per JEDEC JESD36 compliance. Always verify bus pull-up strength (10 kΩ to AVDD) before initialization.
Does LP3907SQX-VRZX/NOPB support dynamic voltage scaling for both buck converters?
Yes, LP3907SQX-VRZX/NOPB supports full dynamic voltage scaling for Buck1 and Buck2 via its I²C interface. The output voltage of each buck can be adjusted in real time across its full range (Buck1: 0.8–2.0 V; Buck2: 1.0–3.5 V) using dedicated VOUT registers. This enables adaptive power management in FPGAs and processors without hardware reconfiguration or external DACs.
What is the minimum input voltage required to operate LP3907SQX-VRZX/NOPB's LDOs?
The LDOs in LP3907SQX-VRZX/NOPB require a minimum input voltage of 1.74 V on their respective VINLDO1 and VINLDO2 pins, as specified in the datasheet's electrical characteristics. This allows direct connection to buck converter outputs (e.g., 1.8-V Buck2 feeding 1.5-V LDO2), provided the dropout margin (≥30 mV typical at 50 mA) is maintained for regulation.
How does the nPOR function work on LP3907SQX-VRZX/NOPB?
The nPOR pin on LP3907SQX-VRZX/NOPB is an open-drain output that remains low until both Buck1 and Buck2 outputs reach ≥94% of their programmed target voltages. It then releases after a 50-ms default delay, signaling stable power to the host system. If either buck drops below 85% of target, nPOR actively pulls low again - providing reliable reset coordination without external circuitry.
Can LP3907SQX-VRZX/NOPB operate with ceramic output capacitors only?
Yes, LP3907SQX-VRZX/NOPB is designed for ceramic-only output capacitors: 10 µF for each buck (SW1/SW2) and 0.47 µF for each LDO (LDO1/LDO2), with ESR ≤500 mΩ. The internal compensation is optimized for low-ESR MLCCs, eliminating need for tantalum or electrolytic capacitors. Using ceramics improves transient response, reduces board area, and enhances reliability over temperature.
LP3907SQX-VRZX/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 24-WFQFN Exposed Pad
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (2), Linear (LDO) (2)
- Number of Outputs:
- 4
- Frequency - Switching:
- 2.1MHz
- Voltage/Current - Output 1:
- 1.8V, 1A
- Voltage/Current - Output 2:
- 2.7V, 600mA
- Voltage/Current - Output 3:
- 3.5V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.8V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 24-WQFN (4x4)
LP3907SQX-VRZX/NOPB FAQ
1.How can I place an order for LP3907SQX-VRZX/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP3907SQX-VRZX/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP3907SQX-VRZX/NOPB reliable?
The price and inventory of LP3907SQX-VRZX/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3907SQX-VRZX/NOPB is usually 5 days.
3.What payment methods are accepted for LP3907SQX-VRZX/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3907SQX-VRZX/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP3907SQX-VRZX/NOPB?
LP3907SQX-VRZX/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP3907SQX-VRZX/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP3907SQX-VRZX/NOPB?
For technical support, including LP3907SQX-VRZX/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3907SQX-VRZX/NOPB requirements.
6.How does Aetrix verify that LP3907SQX-VRZX/NOPB is sourced from the original manufacturer or authorized distributors?
All LP3907SQX-VRZX/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3907SQX-VRZX/NOPB meets industry standards.
7.What is the process for return or replacement of LP3907SQX-VRZX/NOPB?
All LP3907SQX-VRZX/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP3907SQX-VRZX/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP3907SQX-VRZX/NOPB part is unused and in its original packaging.
Return procedure for LP3907SQX-VRZX/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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