Texas Instruments LP3918TL-A/NOPB
- Part No.:
- LP3918TL-A/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Battery Chargers
- Package:
- 25-WFBGA
- Datasheet:
-
LP3918TL-A/NOPB.pdf
- Description:
- IC BATT CHG LI-ION 25USMD
- Quantity:
- Payment:

- Shipping:

Inventory:500
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Product details
Overview
LP3918TL-A/NOPB from Texas Instruments is a fully integrated Li-ion battery charge management and 7-output LDO regulator unit for CDMA handset power systems. It delivers programmable 50–950 mA charging current, seven low-noise LDOs (2×300 mA, 3×150 mA, 2×80 mA), and I²C-compatible serial control - all in a 25-bump 2.5×2.5 mm DSBGA package. It powers baseband processor domains including CORE, DIGI, ANA, TCXO, RX, TX, and GP rails.
For engineers reviewing the LP3918TL-A/NOPB datasheet, LP3918TL-A/NOPB pinout, LP3918TL-A/NOPB application, or LP3918TL-A/NOPB equivalent, key selection considerations include thermal-regulated Li-ion charging compliance, multi-rail LDO sequencing control via I²C, dropout voltage performance across output current grades, and integration of IMON current monitoring and ACOK status signaling.
Technical Context
The LP3918TL-A/NOPB implements a linear CC/CV Li-ion charger with pre-charge, constant-current, constant-voltage, and maintenance modes, thermally regulated to 115°C junction limit. It integrates power FET, reverse-current blocking diode, and sense resistor - requiring no external current-sense components.
All seven LDOs support programmable output voltages (1.5–3.3 V) via I²C interface; LDO1 (CORE, 300 mA), LDO2 (DIGI, 300 mA), and LDO3 (ANA, 80 mA) power up by default in strict sequence, while LDO4–LDO7 are enabled via dedicated pins or serial command. Internal logic is powered from LDO2.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Charging Current Range | 50 mA to 950 mA in 50 mA steps; enables precise battery charge rate tuning per cell capacity and thermal envelope. |
| LDO Output Accuracy | ±2% typical over temperature; ensures stable core/digital/analog rail voltages without external trimming. |
| Dropout Voltage (LDO1) | 200 mV typical at 300 mA; supports high-efficiency regulation even with low VIN–VOUT margin (e.g., 3.6 V → 3.0 V). |
| I²C Interface Speed | 400 kHz maximum clock frequency; compatible with standard microcontroller I²C peripherals for real-time LDO/charger reconfiguration. |
| Input Voltage Range (CHG_IN) | 4.5 V to 6.0 V; matches USB 2.0 (5 V ±5%) and wall adapter specifications for dual-source charging. |
| Package | 25-bump thin DSBGA, 2.5 mm × 2.5 mm; optimized for space-constrained mobile handset PCB layouts with fine-pitch routing. |
| IMON Monitor Output | Analog voltage output: VIMON(mV) = 2.47 × ICHG(mA); provides direct, calibrated current sensing without external amplifier or ADC. |
Pinout & Package
LP3918TL-A/NOPB uses a 25-pin thin DSBGA package (2.5 mm × 2.5 mm, 0.4 mm pitch) with bottom-side solder bumps. Pin mapping follows JEDEC MO-220WGGD2 standard layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1 IMON | Charge current monitor analog output | Provides real-time, proportional voltage representation of fast-charge current (2.47 mV/mA) for system-level fuel gauging or thermal management. |
| A2 PS_HOLD | Digital input for power sequencing control | Held HIGH by host processor to maintain PMU operation; asserted LOW initiates controlled shutdown sequence. |
| A3 VSS | Digital ground reference | Separate digital return path minimizes noise coupling into control logic and I²C interface. |
| A4 RESET_N | Open-drain reset output | Asserted LOW during power-up; goes HIGH 60 ms after LDO1 (CORE) reaches regulation - synchronizes host processor boot timing. |
| A5 ACOK_N | AC adapter presence indicator | Active-low signal pulled LOW when CHG_IN voltage is within 4.5–6.0 V range - enables automatic source selection logic. |
| B1 CHG_IN | DC power input to charger block | Accepts wall/car adapter input; internal UVLO and OVP protect against out-of-spec supply conditions. |
| B2 PWR_ON | Power-on enable input | Internal 500 kΩ pull-down; driven HIGH by host to initiate full power-up sequence including LDO1–LDO3 startup. |
| B3 SCL | I²C clock input | Requires external 1.5 kΩ pull-up; supports standard/fast-mode I²C communication for register read/write operations. |
| B4 PON_N | Inverted PWR_ON output | Active-low mirror of PWR_ON; used for synchronous enable of companion power circuits or discrete switches. |
| C1 BATT | Main battery connection | Direct connection to Li-ion cell anode; carries bidirectional current during charge/discharge cycles. |
| C2 HF_PWR | High-frequency power-up trigger | Alternative wake-up input (500 kΩ pull-down); used for RF subsystem-initiated power-on events. |
| C3 SDA | I²C data input/output (open-drain) | Shared bidirectional bus line; requires external 1.5 kΩ pull-up for proper I²C protocol compliance. |
| C4 TX_EN | LDO6 (TX) enable control | Direct hardware control of transmit-power LDO; allows independent RF PA power gating without I²C overhead. |
| C5 LDO7 | General-purpose LDO output (150 mA) | Programmable 1.5–3.3 V output; default 3.0 V; software-controllable enable/disable via I²C register OP_EN. |
| D1 VIN1 | Input supply for LDO1 and LDO2 | Connected to battery or main rail; powers CORE and DIGI domains - critical for baseband processor stability. |
| D2 TCXO_EN | LDO4 (TCXO) enable control | Hardware-gated enable for temperature-compensated crystal oscillator supply; reduces standby current when TCXO inactive. |
| D3 GNDA | Analog ground reference | Isolated analog return path prevents digital switching noise from degrading LDO noise performance and IMON accuracy. |
| D4 RX_EN | LDO5 (RX) enable control | Direct enable for receive-path LDO; supports burst-mode power control aligned with RF receiver activity. |
| D5 LDO5 | Receive-path LDO output (150 mA) | Supplies RF receiver circuitry; default 3.0 V; programmable via LDO5PGM register; low noise (45 µVRMS) preserves SNR. |
| E1 LDO1 | CORE domain LDO output (300 mA) | Primary power rail for baseband processor core; default 1.8 V; tight 200 mV dropout enables efficient 3.6 V → 1.8 V conversion. |
| E2 LDO2 | DIGI domain LDO output (300 mA) | Supplies digital baseband logic; default 3.0 V; powers internal PMU logic and I²C interface - defines VIH/VIL thresholds. |
| E3 LDO3 | ANA domain LDO output (80 mA) | Low-noise analog supply for audio/ADC circuits; default 3.0 V; 65 dB PSRR at 10 kHz rejects switching noise from adjacent rails. |
| E4 LDO4 | TCXO domain LDO output (80 mA) | Stable, low-noise supply for precision oscillator; default 3.0 V; TCXO_EN pin allows hardware-controlled activation. |
| E5 VIN2 | Input supply for LDO3–LDO7 | Second battery-derived input; decouples analog/RF/GP domains from CORE/DIGI supply path to minimize cross-talk. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Li-ion charger with thermal regulation | Junction temperature limited to 115°C; dynamically reduces charge current above threshold to prevent overheating without external thermal sensors. |
| Seven independently controllable LDOs | Three LDOs (LDO1/LDO2/LDO3) power up by default in fixed sequence; four others (LDO4–LDO7) support hardware or I²C enable - enabling flexible power-state management. |
| I²C-compatible serial interface (7-bit slave address 0x7E) | Enables full configuration of LDO voltages (16 options per rail), charger termination voltage (4.1–4.4 V), EOC threshold (0.1–0.25C), and restart level (50–200 mV below VTERM). |
| Charge current monitor (IMON) with 2.47 mV/mA scaling | Eliminates need for external current-sense amplifier and ADC; supports accurate real-time battery state estimation using single analog input channel. |
| Multi-level power-good signaling (ACOK_N, RESET_N, PON_N) | Provides hardware-level status for AC adapter presence, core rail readiness, and power-on assertion - simplifies system-level power sequencing logic. |
Applications
| CDMA Handset Power Management | Low-Power Wireless Handset |
|---|---|
Use Scenario: Compact CDMA phone requiring simultaneous power to baseband processor (CORE/DIGI), RF transceiver (TX/RX), TCXO, and analog audio blocks. IC Role / Device Role / Timing Role: Single-chip power management unit (PMU) delivering sequenced, regulated rails and thermally managed Li-ion charging. Use Value: Reduces BOM count by integrating 7 LDOs + charger + I²C interface; eliminates discrete charge controller and multiple regulators. |
Use Scenario: Portable VoIP or DECT handset operating from single-cell Li-ion with intermittent RF transmission and long standby time. IC Role / Device Role / Timing Role: Intelligent power manager enabling dynamic LDO enable/disable and USB/adapter charge mode auto-detection. Use Value: Achieves <10 µA system standby via LDO1–LDO3 retention and I²C-controlled disable of unused rails (e.g., TX/RX during idle). |
| Handheld Information Appliance | Digital Camera Backlight & Sensor Supply |
Use Scenario: PDA or e-reader with ARM-based application processor, touchscreen controller, and SD card interface. IC Role / Device Role / Timing Role: Multi-rail regulator supplying core (1.8 V), I/O (3.0 V), analog (3.0 V), and peripheral (3.0 V) domains with precise voltage accuracy. Use Value: ±2% LDO accuracy ensures reliable DDR memory interface timing and ADC reference stability across temperature. |
Use Scenario: Compact digital camera requiring isolated, low-noise supplies for CMOS image sensor (ANA), flash LED driver (GP), and timing oscillator (TCXO). IC Role / Device Role / Timing Role: Dedicated analog/RF power source with 45 µVRMS noise and 65 dB PSRR to preserve image sensor dynamic range. Use Value: Prevents switching noise from digital domains from modulating sensor output - reducing fixed-pattern noise and improving SNR. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar battery charge management and multi-LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| BQ24075RGTR | Single-input Li-ion charger only (no integrated LDOs); requires external regulators for system rails. | Suitable where existing LDO architecture exists and only charger integration is needed. | Select when board space permits separate charger + regulator solution and I²C control of LDOs is unnecessary. |
| TPS65023RSBR | Three buck converters + two LDOs + I²C interface; no integrated Li-ion charger; higher efficiency for >500 mA loads. | Better suited for applications with high-current digital cores and no battery charging requirement. | Choose when primary need is high-efficiency DC/DC conversion and battery charging is handled externally or omitted. |
Compared with BQ24075RGTR and TPS65023RSBR, LP3918TL-A/NOPB uniquely combines full Li-ion charging capability with seven software/hardware-controllable LDOs in one ultra-compact DSBGA package - eliminating inter-rail noise coupling and simplifying power sequencing in space-constrained handsets.
Availability
LP3918TL-A/NOPB is available at Aetrix Electronics and suitable for CDMA handset design, low-power wireless terminal development, and handheld information appliance production requiring stable component supply and long-term lifecycle support.
Supply support for LP3918TL-A/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management ICs for industrial, automotive, and communications markets.
The LP3918TL-A/NOPB belongs to TI's Power Management Unit (PMU) product line, designed specifically for highly integrated, space-constrained mobile devices requiring coordinated battery charging and multi-rail analog/digital power delivery.
FAQ
What is the default output voltage of LDO1 in LP3918TL-A/NOPB?
The default output voltage of LDO1 (CORE) in LP3918TL-A/NOPB is 1.8 V, as specified in Table 1 of the datasheet. This rail powers the baseband processor core and reaches regulation before LDO2 and LDO3 during startup. The LP3918TL-A/NOPB supports reprogramming LDO1 to 1.5–3.3 V via its I²C interface using the LDO1PGM register.
Does LP3918TL-A/NOPB support USB charging mode?
Yes, LP3918TL-A/NOPB supports USB charging mode with programmable 100 mA or 450 mA current limits, selectable via the CHGCNTL1 register. The device detects USB compliance through the CHG_IN voltage range (4.5–6.0 V) and ACOK_N signal assertion. LP3918TL-A/NOPB automatically configures appropriate charge parameters when USB mode is enabled.
How does the IMON pin on LP3918TL-A/NOPB function?
The IMON pin on LP3918TL-A/NOPB provides an analog voltage output directly proportional to the fast-charge current: VIMON(mV) = 2.47 × ICHG(mA). For example, at 450 mA charge current, IMON outputs ~1.112 V. This calibrated output eliminates external sensing components and enables accurate battery fuel gauging in LP3918TL-A/NOPB-based systems.
What is the thermal shutdown threshold for LP3918TL-A/NOPB?
The LP3918TL-A/NOPB features thermal regulation with a junction temperature threshold of 115°C, as specified in the Charger Electrical Characteristics table. When this limit is approached, the device dynamically reduces charge current to maintain safe operating temperature - a feature implemented entirely internally without external thermal feedback. This behavior is active in all charge modes of LP3918TL-A/NOPB.
Can LDO4 (TCXO) be enabled without using the I²C interface on LP3918TL-A/NOPB?
Yes, LDO4 (TCXO) on LP3918TL-A/NOPB can be enabled directly via the TCXO_EN pin (D2), which is a dedicated hardware control input. Driving TCXO_EN HIGH activates the 80 mA TCXO LDO with default 3.0 V output, independent of I²C commands. This allows immediate, low-latency activation of the oscillator supply during RF subsystem wake-up sequences in LP3918TL-A/NOPB designs.
LP3918TL-A/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 25-WFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Battery Chemistry:
- Lithium Ion
- Number of Cells:
- -
- Current - Charging:
- Constant - Programmable
- Programmable Features:
- -
- Fault Protection:
- Reverse Current
- Charge Current - Max:
- 950mA
- Battery Pack Voltage:
- 4.2V
- Voltage - Supply (Max):
- 6V
- Interface:
- I2C
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 25-uSMD
LP3918TL-A/NOPB FAQ
1.How can I place an order for LP3918TL-A/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP3918TL-A/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP3918TL-A/NOPB reliable?
The price and inventory of LP3918TL-A/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3918TL-A/NOPB is usually 5 days.
3.What payment methods are accepted for LP3918TL-A/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3918TL-A/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP3918TL-A/NOPB?
LP3918TL-A/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP3918TL-A/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP3918TL-A/NOPB?
For technical support, including LP3918TL-A/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3918TL-A/NOPB requirements.
6.How does Aetrix verify that LP3918TL-A/NOPB is sourced from the original manufacturer or authorized distributors?
All LP3918TL-A/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3918TL-A/NOPB meets industry standards.
7.What is the process for return or replacement of LP3918TL-A/NOPB?
All LP3918TL-A/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP3918TL-A/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP3918TL-A/NOPB part is unused and in its original packaging.
Return procedure for LP3918TL-A/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LP3918TL-A/NOPB Tags

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BQ21040DBVR
Texas Instruments

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