Texas Instruments LP3928TLX-1828/NOPB
- Part No.:
- LP3928TLX-1828/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Translators, Level Shifters
- Package:
- Datasheet:
-
LP3928TLX-1828/NOPB.pdf
- Description:
- IC TRANSLATOR BIDIR 16DSBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,638
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LP3928TLX-1828/NOPB from Texas Instruments is a dual-function integrated circuit combining a bi-directional level shifter for three independent 1.8V ↔ 2.85V signal paths and an ultra-low-dropout 2.85V LDO regulator delivering up to 150 mA. It features 4-mode logic-controlled enable, 4 ns typical propagation delay, and operates from 3.05V–6.0V input-designed specifically for SD/multi-media card interfaces in space-constrained cellular handsets.
For engineers reviewing the LP3928TLX-1828/NOPB datasheet, LP3928TLX-1828/NOPB pinout, LP3928TLX-1828/NOPB application, or LP3928TLX-1828/NOPB equivalent, key selection considerations include its DSBGA-16 package footprint, direction-controlled latching capability, thermal shutdown integration, ceramic-capacitor compatibility (1.5 µF min), and simultaneous voltage translation + local 2.85V power generation in one die.
Technical Context
The LP3928TLX-1828/NOPB integrates two functionally distinct subsystems on a single die: three independently direction-controlled bi-directional level shifters (A↔B pairs) with 20 ns direction-switch response and 2 µA I/O leakage, plus a standalone CMOS LDO regulator with 100 mV max dropout at 150 mA and 200 µs typical turn-on time. Both subsystems share common ground but are powered from separate rails: VCCA (1.65–1.95V) for the 1.8V-side logic and VBAT (3.05–6.0V) for the LDO input.
Operation modes are selected via EN1/EN2 pins and include full off (both low), LDO-only (EN1=0, EN2=1), latch-bypassed B→A translation (EN1=1, EN2=0), and full active mode with rising-edge latching (EN1=EN2=1). The LatchClk input operates at 2.85V and enables synchronous capture of B-side signals during B→A translation-critical for timing-critical SD card command/data handshaking.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Level Shifter Channels | Three independent bi-directional channels (A1/B1, A2/B2, A3/B3) supporting 1.8V ↔ 2.85V translation |
| Propagation Delay | 4 ns typical (A↔B), enabling high-speed SD card clock domains up to ~100 MHz |
| LDO Output | Fixed 2.85V, ±2% tolerance, stable with 1.5 µF ceramic output capacitor |
| Dropout Voltage | 100 mV maximum at 150 mA load-ensures regulation down to 2.95V input |
| Enable Modes | Four logic-configurable states via EN1/EN2: full off, LDO-only, latch-bypassed, full active with latching |
| Thermal Protection | Integrated thermal shutdown at 160°C with 20°C hysteresis-forces all I/O into high-Z state |
| Package | 16-bump DSBGA (YZR), 0.6 mm pitch, 1.6 mm × 1.6 mm footprint |
Pinout & Package
LP3928TLX-1828/NOPB uses a 16-bump DSBGA (YZR) package with 0.6 mm pitch and 1.6 mm × 1.6 mm body size. Bumps are arranged in a 4×4 grid; pin mapping follows TI's standard bottom-view bump identifier convention (e.g., A1 = bump at row A/column 1).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1, A2, A3 | 1.8V I/O Channel Terminals | Bi-directional signal pins on 1.8V domain; paired with B1/B2/B3 for level translation |
| B1, B2, B3 | 2.85V I/O Channel Terminals | Bi-directional signal pins on 2.85V domain; paired with A1/A2/A3 for level translation |
| DIR1, DIR2, DIR3 | Direction Control Inputs | 1.8V logic inputs setting per-channel direction: '1' = A→B, '0' = B→A |
| VCCA | 1.8V Domain Supply | Power rail for 1.8V-side logic, must be 1.65–1.95V |
| VCCB | LDO Output / 2.85V Rail | Regulated 2.85V output powering B-side I/O and internal latches |
| VBAT | LDO Input | Battery input (3.05–6.0V); supplies both LDO and internal bias circuits |
| GND | Power Ground | Common reference for all analog and digital functions |
| EN1, EN2 | Mode Control Inputs | 1.8V logic pins selecting among four operational states (see Table 1) |
| LatchClk | Latching Clock Input | 2.85V clock input triggering synchronous capture of B-side data during B→A translation |
Key Features
| Feature | Design Value |
|---|---|
| Ultra-small DSBGA footprint | 1.6 mm × 1.6 mm area saves PCB space in mobile phone SD card slots and camera modules |
| Bi-directional level shifting | Three independent channels support simultaneous 1.8V ↔ 2.85V translation without external direction control logic |
| Configurable latching | Rising-edge triggered B→A latching enables deterministic timing for SD command-response sequences |
| Ceramic-capacitor stability | Stable with 1.5 µF ±30% ceramic output cap-eliminates need for larger, costlier tantalum capacitors |
| Integrated thermal shutdown | 160°C trip point disables LDO and forces all I/O into high-Z-prevents damage during sustained overload |
Applications
| SD Card Interface | Multi-Media Card (MMC) Host |
|---|---|
Use Scenario: Interfacing a 1.8V application processor with a 2.85V SD memory card in a smartphone mainboard. IC Role / Device Role / Timing Role: LP3928TLX-1828/NOPB provides bidirectional voltage translation for CMD, CLK, and DAT lines while supplying regulated 2.85V to the SD card's VDD. Use Value: Eliminates need for discrete level shifters and a separate LDO, reducing BOM count by ≥4 components and saving >2.5 mm² PCB area. | Use Scenario: Enabling 1.8V SoC communication with legacy 2.85V MMC devices in portable media players. IC Role / Device Role / Timing Role: LP3928TLX-1828/NOPB acts as protocol-transparent voltage translator and local power source, with DIR pins configured for fixed A→B direction during initialization. Use Value: Supports hot-plug detection and command sequencing via LatchClk-synchronized B→A capture-improving reliability of write-protect and status register reads. |
| Logic Level Translation Module | Portable Information Appliance Power + I/O Hub |
Use Scenario: Bridging 1.8V FPGA I/O banks to 2.85V peripheral ICs (e.g., display drivers, audio codecs) in handheld terminals. IC Role / Device Role / Timing Role: LP3928TLX-1828/NOPB serves as a compact, low-latency translation interface with independent direction control per channel. Use Value: 4 ns propagation delay and 2 ns rise/fall times preserve signal integrity for 50+ MHz parallel buses-avoiding timing closure issues in FPGA designs. | Use Scenario: Consolidating power and signal translation for a 1.8V microcontroller managing multiple 2.85V sensors and actuators in a medical handheld device. IC Role / Device Role / Timing Role: LP3928TLX-1828/NOPB delivers clean 2.85V power and translates GPIO, I²C, and interrupt lines between domains. Use Value: Four enable modes allow dynamic power gating: full shutdown during sleep (EN1=EN2=0) reduces system quiescent current to <20 µA. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bi-directional level shifting and local LDO applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TXS0103D | 3-channel 1.2V–3.6V level shifter only-no integrated LDO; requires external 2.85V supply | Suitable when 2.85V rail already exists; lacks power generation capability | Select TXS0103D if board has dedicated 2.85V supply and only translation is needed-reduces thermal load vs. LP3928TLX-1828/NOPB |
| TPS795285 | Standalone 2.85V LDO only-no level shifting; supports 250 mA output | Used where level translation is handled separately (e.g., discrete MOSFET translators) | Choose TPS795285 when higher LDO current (>150 mA) or lower dropout (<100 mV) is required-requires additional level-shifting solution |
Compared with TXS0103D and TPS795285, LP3928TLX-1828/NOPB uniquely combines both functions in one DSBGA package-reducing component count, interconnect parasitics, and layout complexity for SD/MMC host designs where space and integration are critical.
Availability
LP3928TLX-1828/NOPB is available at Aetrix Electronics and suitable for cellular handset SD card interfaces, multi-media card host controllers, and portable information appliance power + I/O hubs requiring stable component supply across production lifecycles.
Supply support for LP3928TLX-1828/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 50 years of innovation in power management and signal conditioning ICs.
The LP3928TLX-1828/NOPB belongs to TI's portable power and interface solutions product line-designed to integrate voltage translation and local regulation for battery-powered mobile storage interfaces, minimizing PCB area and system-level power loss.
FAQ
What is the maximum operating temperature range for the LP3928TLX-1828/NOPB?
The LP3928TLX-1828/NOPB is specified for junction temperatures from −40°C to +125°C and ambient temperatures from −40°C to +85°C. Its integrated thermal shutdown activates at 160°C with 20°C hysteresis, forcing all I/O into high-Z state to protect downstream circuitry. This makes LP3928TLX-1828/NOPB suitable for enclosed handheld devices where thermal dissipation is constrained.
Can the LP3928TLX-1828/NOPB operate with an external 2.85V supply instead of using its internal LDO?
Yes-the LP3928TLX-1828/NOPB supports external VCCB supply in the range of 1.65V to 3.6V. When VCCB is externally supplied, the internal LDO is bypassed, and only its quiescent current contributes to total consumption. This configuration is valid only when both VBAT and VCCB are connected to the same external source, as stated in the Operating Conditions section. LP3928TLX-1828/NOPB maintains full level-shifting functionality in this mode.
How does the LatchClk function interact with direction control in the LP3928TLX-1828/NOPB?
In LP3928TLX-1828/NOPB, LatchClk only affects B→A translation (DIRx = 0) and is active only in full ON mode (EN1 = EN2 = 1). A rising edge on LatchClk captures the current logic level at Bx and updates Ax synchronously-enabling precise timing alignment for SD card command responses. When DIRx = 1 (A→B), LatchClk has no effect. LP3928TLX-1828/NOPB ensures setup/hold times of 1–2 ns relative to the clock edge.
What output capacitor types and values are validated for stable operation of the LP3928TLX-1828/NOPB LDO?
The LP3928TLX-1828/NOPB LDO is characterized as stable with ceramic capacitors from 1.5 µF to 22 µF (±30%) and ESR from 5 mΩ to 500 mΩ. X7R dielectric ceramics are recommended for temperature stability (±15% capacitance shift from −40°C to +85°C). Tantalum capacitors are supported but require higher ESR tolerance and surge-current rating-LP3928TLX-1828/NOPB remains stable with no-load conditions, critical for RAM keep-alive applications.
Is the LP3928TLX-1828/NOPB pin-compatible with other members of the LP3928 family?
Yes-LP3928TLX-1828/NOPB shares identical pinout, package (DSBGA-16 YZR), and electrical behavior with all LP3928 variants (e.g., LP3928TLX-2828/NOPB), differing only in factory-trimmed LDO output voltage (2.85V here). Direction control, enable logic, level-shifting performance, and thermal protection are identical across the family. This allows drop-in replacement when 2.85V regulation is required, without PCB or firmware changes.
LP3928TLX-1828/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Translator Type:
- Voltage Level
- Channel Type:
- Bidirectional
- Number of Circuits:
- 1
- Channels per Circuit:
- 3
- Voltage - VCCA:
- 1.65 V ~ 1.95 V
- Voltage - VCCB:
- 1.65 V ~ 3.6 V
- Input Signal:
- -
- Output Signal:
- -
- Output Type:
- Tri-State, Non-Inverted
- Data Rate:
- -
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Features:
- SIM Card Interface
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-WFBGA
LP3928TLX-1828/NOPB FAQ
1.How can I place an order for LP3928TLX-1828/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP3928TLX-1828/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP3928TLX-1828/NOPB reliable?
The price and inventory of LP3928TLX-1828/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3928TLX-1828/NOPB is usually 5 days.
3.What payment methods are accepted for LP3928TLX-1828/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3928TLX-1828/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP3928TLX-1828/NOPB?
LP3928TLX-1828/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP3928TLX-1828/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP3928TLX-1828/NOPB?
For technical support, including LP3928TLX-1828/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3928TLX-1828/NOPB requirements.
6.How does Aetrix verify that LP3928TLX-1828/NOPB is sourced from the original manufacturer or authorized distributors?
All LP3928TLX-1828/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3928TLX-1828/NOPB meets industry standards.
7.What is the process for return or replacement of LP3928TLX-1828/NOPB?
All LP3928TLX-1828/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP3928TLX-1828/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP3928TLX-1828/NOPB part is unused and in its original packaging.
Return procedure for LP3928TLX-1828/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LP3928TLX-1828/NOPB Tags

-
74LVC1T45GW,125
Nexperia USA Inc.
-
74LVCH2T45DC,125
Nexperia USA Inc.

-
SN74LVC1T45DBVR
Texas Instruments

-
SN74LVC1T45DRLR
Texas Instruments

-
SN74LVC1T45DPKR
Texas Instruments

-
SN74LVC2T45DCTR
Texas Instruments

-
74LVC2T45GT,115
Nexperia USA Inc.

-
SN74LVC1T45YZPR
Texas Instruments

-
LSF0102DCUR
Texas Instruments

-
SN74LVC1T45DCKR
Texas Instruments

-
TXS0102DCTR
Texas Instruments

-
FXLP34P5X
onsemi
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

