Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Power Management (PMIC) > Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

Texas Instruments LP3985IM5-2.8

Name: LP3985IM5-2.8
Brand: Texas Instruments
SKU: LP3985IM5-2.8
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: LP3985IM5-2.8

Manufacturer:: Texas Instruments

Category:: Voltage Regulators - Linear, Low Drop Out (LDO) Regulators

Package:: SC-74A, SOT-753

Datasheet:: LP3985IM5-2.8.pdf

Description:: IC REG LINEAR 2.8V 150MA SOT23-5

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:4,702

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

LP3985IM5-2.8 from Texas Instruments is a fixed-output, micropower, ultra-low-dropout CMOS voltage regulator delivering 150 mA at 2.8 V with ≤100 mV dropout at full load, 30 µVRMS output noise (10 Hz–100 kHz), and 50 dB PSRR at 1 kHz - optimized for RF power amplifier biasing and low-noise analog supply in cellular handsets.

For engineers reviewing the LP3985IM5-2.8 datasheet, LP3985IM5-2.8 pinout, LP3985IM5-2.8 application, or LP3985IM5-2.8 equivalent, key selection criteria include verified 2.8-V output tolerance (±3%), shutdown current ≤1.5 µA, DSBGA-5 package footprint (1.502 mm × 1.045 mm), and compatibility with 1-µF ceramic output capacitors without external compensation.

Technical Context

The LP3985IM5-2.8 uses a PMOS pass transistor architecture enabling ultra-low dropout and minimal ground current variation across load (85 µA at 0 mA → 140 µA at 150 mA). Its internal 1.23-V bandgap reference and fast-turnon circuit pre-charges the BYPASS pin via a 70-µA current source to achieve 200 µs startup time.

It integrates thermal shutdown (160°C trip, 20°C hysteresis) and short-circuit current limiting (600 mA steady-state), operates from 2.5 V to 6 V input, and maintains stability with 1-µF ±30% ceramic or high-quality tantalum output capacitors - no ESR requirements.

Key Specifications

Parameter	Value and Actual Design Meaning
Output Voltage	Fixed 2.8 V ±3% over −40°C to 125°C junction temperature - ensures stable bias for 2.8-V RF PA stages without external feedback.
Max Dropout Voltage	100 mV at 150 mA load - enables operation down to VIN = 2.9 V, critical for single-cell Li-ion (3.0–4.2 V) systems under discharge.
Quiescent Current	140 µA typical at 150 mA load; ≤1.5 µA in shutdown - extends battery life in always-on standby modes of mobile handsets.
Output Noise	30 µVRMS (10 Hz–100 kHz) with 0.01 µF BYPASS capacitor - meets stringent noise requirements for GSM/CDMA/WCDMA RF front-end power rails.
PSRR	50 dB at 1 kHz, VIN = VOUT + 0.2 V - suppresses switching noise from upstream DC-DC converters feeding the LDO input.
Enable Threshold	VIH = 1.4 V, VIL = 0.4 V - compatible with 1.8-V and 2.8-V logic interfaces for controlled power sequencing.
Thermal Protection	160°C shutdown with 20°C hysteresis - prevents permanent damage during sustained overload or poor PCB thermal design.

Pinout & Package

LP3985IM5-2.8 is packaged in a 5-pin DSBGA (YZR) with body size 1.502 mm × 1.045 mm (MAX), requiring minimal PCB area (<2 mm × 2.5 mm total circuit footprint).

Pin/Terminal	Circuit Role	Design Meaning
BYPASS (A3)	I/O	Connects to 0.01 µF capacitor to reduce output noise; internally pre-charged for fast turn-on - enables simultaneous low-noise and rapid enable response.
IN (C3)	Input	Accepts 2.5–6 V unregulated input; requires ≥1 µF ceramic capacitor placed within 1 cm of pin for stability and transient immunity.
EN (A1)	Digital Input	Logic-controlled enable: high ≥1.4 V enables regulator; low ≤0.4 V disables with ≤1.5 µA shutdown current - supports system-level power gating.
GND (B2)	Ground	Common return path for IN, OUT, EN, and BYPASS; must connect to clean analog ground plane to preserve PSRR and noise performance.
OUT (C1)	Output	Delivers regulated 2.8 V up to 150 mA; stable with 1 µF ceramic capacitor (X7R/X5R); placement within 1 cm of pin minimizes impedance.

Key Features

Feature	Design Value
Ultra-Low-Noise Regulation	30 µVRMS output noise (10 Hz–100 kHz) with optional 0.01 µF BYPASS cap - preserves SNR in sensitive RF receiver chains and ADC reference supplies.
Micro-Power Shutdown	≤1.5 µA quiescent current when EN = low - eliminates leakage during deep sleep, critical for multi-day battery life in portable devices.
DSBGA-5 Miniaturization	1.502 mm × 1.045 mm footprint - enables placement directly beneath RF ICs or in tight space-constrained modules like M.2 or LPWA IoT nodes.
Fast Turn-On Time	200 µs from EN high to 95% VOUT - supports burst-mode operation in TDMA-based systems (GSM, CDMA) requiring rapid rail activation.
Robust Protection	Integrated thermal shutdown (160°C) and short-circuit current limit (600 mA) - eliminates need for external fault management circuitry.

Applications

CDMA/WCDMA RF Power Amplifier Bias	GSM Transmitter Chain Supply
Use Scenario: Providing clean, low-noise 2.8-V bias to GaAs or pHEMT power amplifiers in CDMA/WCDMA handsets operating at 800/1900 MHz. IC Role / Device Role / Timing Role: Low-noise LDO regulator supplying stable V_PA rail; BYPASS pin actively reduces phase noise contribution to adjacent channel leakage. Use Value: 30 µVRMS noise and 50 dB PSRR prevent AM-to-PM distortion and maintain ACLR >45 dB, meeting 3GPP TS 25.101 requirements.	Use Scenario: Delivering regulated 2.8-V supply to GSM PA driver and final stage during TDMA transmit bursts (577 µs on, 4.615 ms off). IC Role / Device Role / Timing Role: Fast-turnon LDO activated by baseband processor's EN signal synchronized to TX slot timing. Use Value: 200 µs startup ensures full VOUT regulation before PA ramp-up begins, eliminating transmit power droop and spectral mask violations.
Portable Audio Codec Reference Supply	Low-Power MCU Core Voltage
Use Scenario: Generating ultra-low-noise 2.8-V reference for stereo audio DACs and ADCs in Bluetooth headsets and wearables. IC Role / Device Role / Timing Role: Precision analog LDO decoupling digital switching noise from audio signal path; GND pin routed to isolated analog ground. Use Value: 30 µVRMS noise and <±3% output tolerance ensure THD+N <−95 dB and consistent dynamic range across battery discharge cycle.	Use Scenario: Supplying 2.8-V core voltage to ARM Cortex-M0+ microcontrollers in energy-harvesting sensor nodes with intermittent wake-up cycles. IC Role / Device Role / Timing Role: Micropower LDO enabled only during active computation; shutdown current ≤1.5 µA minimizes quiescent drain between events. Use Value: 140 µA load current at 150 mA and sub-µA shutdown extend coin-cell lifetime beyond 5 years in duty-cycled applications.

CDMA/WCDMA RF Power Amplifier Bias

GSM Transmitter Chain Supply

Use Scenario: Providing clean, low-noise 2.8-V bias to GaAs or pHEMT power amplifiers in CDMA/WCDMA handsets operating at 800/1900 MHz.

IC Role / Device Role / Timing Role: Low-noise LDO regulator supplying stable V_PA rail; BYPASS pin actively reduces phase noise contribution to adjacent channel leakage.

Use Value: 30 µVRMS noise and 50 dB PSRR prevent AM-to-PM distortion and maintain ACLR >45 dB, meeting 3GPP TS 25.101 requirements.

Use Scenario: Delivering regulated 2.8-V supply to GSM PA driver and final stage during TDMA transmit bursts (577 µs on, 4.615 ms off).

IC Role / Device Role / Timing Role: Fast-turnon LDO activated by baseband processor's EN signal synchronized to TX slot timing.

Use Value: 200 µs startup ensures full VOUT regulation before PA ramp-up begins, eliminating transmit power droop and spectral mask violations.

Portable Audio Codec Reference Supply

Low-Power MCU Core Voltage

Use Scenario: Generating ultra-low-noise 2.8-V reference for stereo audio DACs and ADCs in Bluetooth headsets and wearables.

IC Role / Device Role / Timing Role: Precision analog LDO decoupling digital switching noise from audio signal path; GND pin routed to isolated analog ground.

Use Value: 30 µVRMS noise and <±3% output tolerance ensure THD+N <−95 dB and consistent dynamic range across battery discharge cycle.

Use Scenario: Supplying 2.8-V core voltage to ARM Cortex-M0+ microcontrollers in energy-harvesting sensor nodes with intermittent wake-up cycles.

IC Role / Device Role / Timing Role: Micropower LDO enabled only during active computation; shutdown current ≤1.5 µA minimizes quiescent drain between events.

Use Value: 140 µA load current at 150 mA and sub-µA shutdown extend coin-cell lifetime beyond 5 years in duty-cycled applications.

Equivalent & Alternatives

The following parts are listed as comparable options for similar low-noise LDO regulator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
TPL720F28	2.8-V fixed output, 200-mA rating, 55 µVRMS noise, 65 dB PSRR at 1 kHz, SOT-23-5 package	Higher PSRR and output current but larger 2.9 mm × 1.6 mm footprint; requires 2.2 µF output capacitor	Preferred where higher PSRR and current headroom justify larger board area and added cost
MCP1804T-2802I/OT	2.8-V fixed output, 150-mA rating, 45 µVRMS noise, 40 dB PSRR at 1 kHz, SOT-23-5 package	Wider dropout (250 mV @ 150 mA), higher quiescent current (3 µA shutdown), no BYPASS pin for noise reduction	Suitable for cost-sensitive industrial controls where ultra-low noise is non-critical and space constraints less severe

Compared with TPL720F28 and MCP1804T-2802I/OT, the LP3985IM5-2.8 uniquely balances ultra-miniature DSBGA packaging, industry-leading 30 µVRMS noise, and 200 µs turn-on - making it optimal for space- and noise-constrained RF and portable audio designs where every µV and µm matters.

Availability

LP3985IM5-2.8 is available at Aetrix Electronics and suitable for CDMA/WCDMA handset design, GSM transmitter chain implementation, portable audio codec reference supply, and low-power MCU core voltage regulation requiring stable component supply across long-lifecycle consumer electronics programs.

Supply support for LP3985IM5-2.8 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, designing and manufacturing analog and embedded processing chips for industrial, automotive, and personal electronics markets.

The LP3985IM5-2.8 belongs to TI's micropower LDO family engineered specifically for battery-powered wireless devices demanding ultra-low noise, minimal footprint, and fast enable response - targeting cellular handsets, portable medical sensors, and compact IoT edge nodes.

FAQ

What is the maximum input voltage rating for the LP3985IM5-2.8?

The LP3985IM5-2.8 has an absolute maximum input voltage rating of 6.5 V, with recommended operating input range from 2.5 V to 6 V. Exceeding 6.5 V risks permanent damage per Absolute Maximum Ratings. For reliable operation, VIN must be ≥2.8 V + rated dropout (100 mV max), i.e., ≥2.9 V at 150 mA load. The LP3985IM5-2.8 datasheet specifies this in Section 6.1 and 6.3.

Does the LP3985IM5-2.8 require an external bypass capacitor to meet its 30 µVRMS noise specification?

Yes - the 30 µVRMS output noise (10 Hz–100 kHz) is measured with a 0.01 µF capacitor connected to the BYPASS pin. Without this capacitor, typical output noise rises to 230 nV/√Hz broadband density. The LP3985IM5-2.8's internal fast-turnon circuit actively pre-charges this capacitor, so omitting it degrades both noise performance and startup time. This is confirmed in Sections 7.3.3 and 6.5 of the LP3985IM5-2.8 datasheet.

Can the LP3985IM5-2.8 operate stably with a 1-µF X5R ceramic capacitor on the output?

Yes - the LP3985IM5-2.8 is explicitly characterized and guaranteed stable with 1-µF ±30% ceramic capacitors, including X5R dielectrics, as stated in Section 1 (Features) and Section 8.2.2.3. However, X5R exhibits narrower temperature range (−55°C to +85°C) versus X7R (−55°C to +125°C); for extended temperature applications, X7R is preferred. The LP3985IM5-2.8 does not require minimum ESR, simplifying capacitor selection.

What is the thermal shutdown behavior of the LP3985IM5-2.8?

The LP3985IM5-2.8 activates thermal shutdown at 160°C junction temperature with 20°C hysteresis, meaning it resumes regulation only after cooling to ≤140°C. This protection is fully integrated and requires no external components. Thermal shutdown is documented in Section 6.5 (Electrical Characteristics) and Section 7.4.1 of the LP3985IM5-2.8 datasheet, and applies identically across DSBGA and SOT-23 packages.

Is the LP3985IM5-2.8 pin-compatible with other variants in the LP3985 family, such as LP3985IM5-3.0?

Yes - all LP3985IM5-x.x variants share identical DSBGA-5 (YZR) package pinout, terminal functions, and footprint. Pin assignments (IN, OUT, EN, GND, BYPASS) and mechanical dimensions (1.502 mm × 1.045 mm) are identical across output voltages from 2.5 V to 5 V. This allows direct substitution in layout without PCB revision, as confirmed in the "Device Information" table and Pin Configuration section of the LP3985IM5-2.8 datasheet.

LP3985IM5-2.8 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: -

Package/Case:: SC-74A, SOT-753

Packaging:: Tape & Reel (TR)

Product Status:: Obsolete

Output Configuration:: Positive

Output Type:: Fixed

Number of Regulators:: 1

Voltage - Input (Max):: 6V

Voltage - Output (Min/Fixed):: 2.8V

Voltage - Output (Max):: -

Voltage Dropout (Max):: 0.1V @ 150mA

Current - Output:: 150mA

Current - Quiescent (Iq):: 150 µA

Current - Supply (Max):: 250 µA

PSRR:: 50dB ~ 40dB (1kHz ~ 10kHz)

Control Features:: Enable

Protection Features:: Over Current, Over Temperature, Short Circuit

Operating Temperature:: -40°C ~ 125°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: SOT-23-5

LP3985IM5-2.8 FAQ

1.How can I place an order for LP3985IM5-2.8 through Aetrix?

Please submit a Request for Quotation (RFQ) for LP3985IM5-2.8 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for LP3985IM5-2.8 reliable?

The price and inventory of LP3985IM5-2.8 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP3985IM5-2.8 is usually 5 days.

3.What payment methods are accepted for LP3985IM5-2.8?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP3985IM5-2.8 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for LP3985IM5-2.8?

LP3985IM5-2.8 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your LP3985IM5-2.8 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for LP3985IM5-2.8?

For technical support, including LP3985IM5-2.8 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP3985IM5-2.8 requirements.

6.How does Aetrix verify that LP3985IM5-2.8 is sourced from the original manufacturer or authorized distributors?

All LP3985IM5-2.8 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP3985IM5-2.8 meets industry standards.

7.What is the process for return or replacement of LP3985IM5-2.8?

All LP3985IM5-2.8 units undergo pre-shipment inspection (PSI). If there is an issue with LP3985IM5-2.8, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The LP3985IM5-2.8 part is unused and in its original packaging.

Return procedure for LP3985IM5-2.8:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-03 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-01 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…

2026-08-21 What Is an LED Driver? Types, Circuits, Dimming, and Selection

An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…

2026-08-18 Operational Amplifier (Op Amp): Basics, Configurations, Feedback and Applications

Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…

2026-08-14 Jumper Cables: How to Use, Connect and Choose Them Safely

Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…