Texas Instruments LP3996SD-3333/NOPB

Overview

LP3996SD-3333/NOPB from Texas Instruments is a dual fixed-output LDO regulator delivering 3.3 V / 300 mA (LDO2) and 3.3 V / 150 mA (LDO1), with independent enable control, power-on-reset (POR) output, and ultra-low 35 µA quiescent current. It operates from 2.0 V to 6.0 V input and is optimized for space-constrained portable electronics requiring stable dual-rail power and system reset signaling.

For engineers reviewing the LP3996SD-3333/NOPB datasheet, LP3996SD-3333/NOPB pinout, LP3996SD-3333/NOPB application, or LP3996SD-3333/NOPB equivalent, key selection considerations include its dual 3.3 V outputs with asymmetric current capability, adjustable POR delay via external capacitor on SET pin, stability with 1 µF ceramic output capacitors, and WSON-10 (3 mm × 3 mm) lead-free package.

Technical Context

The LP3996SD-3333/NOPB integrates two independent LDO regulators sharing a common input but featuring separate EN1/EN2 controls - enabling flexible power sequencing and partial shutdown. LDO2 includes an internal voltage monitor feeding an open-drain POR output that asserts low when VOUT2 drops below 88% of nominal (2.904 V), releasing high at ≥96% (3.168 V).

Its POR delay is programmable via a capacitor from SET pin to GND, leveraging a 1.25 V threshold and 1.3 µA internal current source (t_DELAY ≈ 1.25 V × C_SET / 1.3 µA); a 0.1 µF capacitor yields ~100 ms delay. The CBYP pin accepts a 10 nF bypass capacitor to reduce reference noise and improve PSRR (70 dB @ 1 kHz for LDO2) and line transient response.

Key Specifications

Pinout & Package

LP3996SD-3333/NOPB uses a 10-pin WSON (Wafer-Level Small Outline No-Lead) package with 3 mm × 3 mm footprint and exposed thermal pad (connected to Pin 6/GND). The package is RoHS-compliant, lead-free, and moisture-sensitivity level 1 (260°C peak reflow).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar dual-LDO-with-POR applications.

Compared with TPL7407LPGQ and TPS79933DDCT, LP3996SD-3333/NOPB uniquely integrates dual 3.3 V LDOs with asymmetric current ratings and a configurable POR output - enabling simpler, smaller, and more reliable power sequencing in portable and embedded systems without external support components.

Availability

LP3996SD-3333/NOPB is available at Aetrix Electronics and suitable for wireless handsets, portable medical sensors, industrial gateways, smart home hubs, and battery-backed IoT edge nodes requiring stable dual 3.3 V supply with integrated power-on-reset functionality.

Supply support for LP3996SD-3333/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of expertise in high-reliability, low-power IC design for industrial, automotive, and consumer markets.

The LP3996SD-3333/NOPB belongs to TI's precision low-dropout linear regulator family, engineered specifically for space- and power-constrained portable electronics needing dual regulated rails and deterministic system reset behavior.

FAQ

What output voltages does the LP3996SD-3333/NOPB provide?

The LP3996SD-3333/NOPB provides two fixed 3.3 V outputs: VOUT1 delivers up to 150 mA, and VOUT2 delivers up to 300 mA. Both outputs are factory-trimmed to ±1.5% accuracy at room temperature and maintain ±3% over –40°C to +125°C junction temperature. The "3333" in the part number explicitly denotes the 3.3 V / 3.3 V configuration.

How is the power-on-reset (POR) delay set on the LP3996SD-3333/NOPB?

The POR delay on the LP3996SD-3333/NOPB is set by connecting a capacitor between the SET pin (Pin 5) and GND. The internal 1.3 µA current source charges this capacitor to a 1.25 V threshold; delay time is calculated as t_DELAY ≈ (1.25 V × C_SET) / 1.3 µA. For example, a 0.1 µF capacitor yields approximately 100 ms delay. Leaving SET open disables POR delay entirely.

Can the LP3996SD-3333/NOPB operate with ceramic output capacitors?

Yes, the LP3996SD-3333/NOPB is designed for stability with 1.0 µF ceramic output capacitors (X7R, X5R, or Y5V dielectrics) having ESR between 5 mΩ and 500 mΩ. This eliminates the need for larger, more expensive tantalum capacitors and reduces total solution size - a key advantage for portable designs where board space is constrained.

What is the quiescent current of the LP3996SD-3333/NOPB in enabled and disabled states?

In enabled state (both LDOs active), the LP3996SD-3333/NOPB draws 35 µA typical quiescent current. When both EN1 and EN2 are pulled low, it enters ultra-low-power shutdown mode drawing less than 10 nA - making it ideal for battery-powered applications requiring long-term standby with rapid wake-up capability.

What package type and thermal characteristics does the LP3996SD-3333/NOPB use?

The LP3996SD-3333/NOPB uses a 10-pin WSON package (3 mm × 3 mm, Package Drawing DSC) with exposed thermal pad. Its junction-to-ambient thermal resistance (θ_JA) is 55°C/W under standard JEDEC conditions. Proper PCB layout - including thermal vias under the exposed pad connected to a solid GND plane - is essential to maintain safe junction temperatures under full load.