Texas Instruments LP5952TLX-1.3/NOPB
- Part No.:
- LP5952TLX-1.3/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 5-WFBGA, DSBGA
- Datasheet:
-
LP5952TLX-1.3/NOPB.pdf
- Description:
- IC REG LINEAR 1.3V 350MA 5DSBGA
- Quantity:
- Payment:

- Shipping:

Inventory:2,819
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LP5952TLX-1.3/NOPB from Texas Instruments is a dual-rail linear regulator designed for ultralow-voltage post-regulation in battery-powered systems, delivering a fixed 1.3 V output at up to 350 mA. It operates with two independent supply rails: VBATT (2.5–5.5 V) powers internal circuitry, while VIN (0.7–4.5 V) supplies the regulated output path. Its 100 µVRMS output noise, ±1 mV line transient response, and 0.1 µA shutdown current make it suitable for powering sensitive RF or analog circuitry in mobile handsets.
For engineers reviewing the LP5952TLX-1.3/NOPB datasheet, LP5952TLX-1.3/NOPB pinout, LP5952TLX-1.3/NOPB application, or LP5952TLX-1.3/NOPB equivalent, key selection criteria include dual-supply rail compatibility, dropout voltage under 1.3 V at 350 mA, thermal shutdown at 165°C, PSRR >90 dB at 100 Hz on VIN, and DSBGA-5 package suitability for space-constrained portable designs.
Technical Context
The LP5952TLX-1.3/NOPB implements a dual-rail architecture where VBATT powers bias circuitry and VIN feeds the NFET pass device - VIN must never exceed VBATT. Its internal thermal shutdown triggers at 165°C (20°C hysteresis) and overcurrent protection limits peak output to 500 mA before thermal foldback engages.
It supports no-load stability and fast startup (70–150 µs), with reverse-current protection managed via the NFET's parasitic body diode - external Schottky clamping is required if VOUT exceeds VIN by more than ~0.3 V with >50 mA reverse current.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Voltage | Fixed 1.3 V ±2% tolerance ensures stable core voltage for low-power microcontrollers and RF ICs. |
| Max Output Current | 350 mA continuous delivery supports baseband processors or sensor hubs without thermal derating in DSBGA-5. |
| Dropout Voltage (VBATT) | ≤1.3 V at 150 mA enables operation down to 2.6 V battery voltage in Li-ion systems. |
| Quiescent Current (VBATT) | 50 µA typical minimizes standby drain in always-on subsystems like real-time clocks. |
| Output Noise | 100 µVRMS (10 Hz–100 kHz) prevents interference in precision ADCs or PLL reference paths. |
| PSRR (VIN, 100 Hz) | 90 dB suppresses switching noise from upstream DC-DC converters feeding the IN rail. |
| Shutdown Current | 0.1 µA typical allows multi-week battery shelf life in powered-off portable instruments. |
Pinout & Package
LP5952TLX-1.3/NOPB is packaged in a 1.326 mm × 0.96 mm, 5-pin DSBGA (YZR) package with 0.4-mm pitch and bottom-side solder balls. The package is optimized for minimal PCB area and thermal performance in thin-profile handheld devices.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| BATT | Bias supply input | Connects to battery (2.5–5.5 V); powers internal LDO control, bandgap, and protection circuits - must be ≥VIN at all times. |
| IN | Power input to pass device | Feeds NFET source; accepts 0.7–4.5 V from DC-DC converter output; VIN ≤ VBATT enforced by design. |
| GND | Analog/digital ground | Common return for all supplies and load; requires low-impedance connection to minimize noise coupling. |
| EN | Enable logic input | Active-high control: VIH ≥1 V enables regulation; VIL ≤0.4 V forces 0.1 µA shutdown - must not float. |
| OUT | Regulated output | Delivers fixed 1.3 V to load; requires 2.2 µF ceramic capacitor (3–300 mΩ ESR) for stability. |
Key Features
| Feature | Design Value |
|---|---|
| Dual-rail supply architecture | Separates bias (VBATT) and power (VIN) paths to enable ultra-low-input-voltage operation without compromising control stability. |
| No-load regulation | Maintains 1.3 V output with zero load current - critical for CMOS RAM keep-alive and wake-up circuitry. |
| Fast startup time | 70–150 µs EN-to-95% VOUT transition enables rapid subsystem activation in responsive user interfaces. |
| Thermal shutdown with hysteresis | 165°C trip point + 20°C hysteresis prevents latch-up during momentary overload while allowing recovery after cooling. |
| Reverse current limiting | Parasitic body diode conducts ≤50 mA reverse current; external Schottky required beyond that to prevent backfeed damage. |
Applications
| Mobile Handset Power Management | Portable Medical Sensor Hub |
|---|---|
Use Scenario: Powers baseband processor core and RF transceiver LNA stages from single Li-ion cell with tight noise and transient requirements. IC Role / Device Role / Timing Role: Dual-rail post-regulator providing clean 1.3 V rail isolated from noisy DC-DC converter output and battery voltage sag. Use Value: 90 dB PSRR at 100 Hz rejects switching ripple; ±1 mV line transient response prevents digital corruption during cellular transmit bursts. | Use Scenario: Supplies ultra-low-power analog front-end (AFE) and low-energy Bluetooth LE SoC in wearable ECG monitor. IC Role / Device Role / Timing Role: Primary voltage regulator delivering stable 1.3 V to precision op-amps and SAR ADC reference buffers. Use Value: 100 µVRMS output noise avoids signal degradation; 50 µA quiescent current extends battery runtime beyond 7 days. |
| Industrial Handheld Scanner | Smart IoT Edge Node |
Use Scenario: Regulates power to laser driver and image sensor in barcode scanner operating from 3-cell NiMH battery. IC Role / Device Role / Timing Role: Dual-input linear regulator maintaining 1.3 V under wide VBATT (3.0–4.5 V) and VIN (1.0–2.5 V) variation during motor actuation. Use Value: Dropout ≤1.3 V at 150 mA sustains regulation as battery discharges; thermal shutdown protects during extended scan duty cycles. | Use Scenario: Provides always-on 1.3 V supply to RTC, memory retention, and wake-up controller in battery-backed edge node. IC Role / Device Role / Timing Role: Low-quiescent, no-load-stable regulator enabling sub-µA system sleep mode with instant wake capability. Use Value: 0.1 µA shutdown current preserves coin-cell energy; no-load stability eliminates need for dummy load resistors. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-rail linear regulator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TLC7701QDCKR | Single-rail, 1.3 V fixed output; no VBATT bias rail; higher 120 µA IQ; requires external enable pull-up. | Lacks dual-rail architecture - unsuitable for post-DC-DC regulation where VIN < VBATT is mandatory. | Select only when system uses single supply and thermal/PSRR specs are secondary to cost. |
| TPS7A1633DRBR | Single-input, 1.3 V LDO; 25 µA IQ; 300 mA max; no thermal hysteresis; different pinout and package (SON-8). | Cannot replace LP5952TLX-1.3/NOPB in dual-rail topologies - no VBATT input or VIN ≤ VBATT enforcement. | Consider only for new designs where board layout allows SON-8 and dual-rail functionality is unnecessary. |
Compared with TLC7701QDCKR and TPS7A1633DRBR, LP5952TLX-1.3/NOPB uniquely supports true dual-rail operation with guaranteed VIN ≤ VBATT sequencing, enabling lower-system-noise architectures in battery-powered RF and precision analog applications where competing single-rail LDOs fail to meet supply-domain isolation requirements.
Availability
LP5952TLX-1.3/NOPB is available at Aetrix Electronics and suitable for mobile handsets, portable medical sensors, industrial scanners, and smart IoT edge nodes requiring stable component supply across long-lifecycle production programs.
Supply support for LP5952TLX-1.3/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and power management technologies for industrial, automotive, and consumer markets.
The LP5952 product line was developed specifically for ultralow-voltage dual-rail post-regulation in space-constrained, battery-powered portable electronics - targeting applications where traditional single-rail LDOs cannot meet simultaneous low-noise, low-dropout, and multi-supply sequencing demands.
FAQ
What is the maximum allowable voltage difference between VBATT and VIN for LP5952TLX-1.3/NOPB?
The LP5952TLX-1.3/NOPB requires VIN ≤ VBATT at all times. Absolute maximum ratings specify VBATT – VIN ≥ 0.2 V; exceeding this risks undefined behavior or damage. In practice, design margin should maintain VBATT ≥ VIN + 0.3 V across temperature and load to ensure reliable operation of the internal bias circuitry and pass device control loop. This constraint is fundamental to the dual-rail architecture of LP5952TLX-1.3/NOPB.
Can LP5952TLX-1.3/NOPB operate with no output load connected?
Yes, LP5952TLX-1.3/NOPB maintains regulation and stability with zero load current - a feature explicitly verified in its datasheet and critical for applications like RTC backup or memory keep-alive. Unlike many LDOs requiring minimum load for stability, LP5952TLX-1.3/NOPB uses an internal compensation scheme that ensures 1.3 V output accuracy and noise performance even under no-load conditions, eliminating the need for dummy resistors in LP5952TLX-1.3/NOPB designs.
What is the recommended output capacitor for LP5952TLX-1.3/NOPB and why?
TI specifies a 2.2 µF ceramic capacitor (X7R dielectric preferred) with ESR between 3 mΩ and 300 mΩ for LP5952TLX-1.3/NOPB. This value ensures phase margin >45° across –40°C to +125°C and load steps up to 350 mA. Smaller values risk instability; larger capacitances are acceptable but offer diminishing returns. The capacitor must be placed within 1 cm of the OUT and GND pins, directly on the bottom side of the DSBGA-5 package, to maintain LP5952TLX-1.3/NOPB's specified transient response and noise performance.
Does LP5952TLX-1.3/NOPB support reverse current protection without external components?
LP5952TLX-1.3/NOPB provides limited reverse current protection via the inherent parasitic body diode of its internal NFET. It safely conducts ≤50 mA from OUT to VIN if VOUT exceeds VIN. Beyond that threshold, uncontrolled reverse current can cause overheating or latch-up. Therefore, an external Schottky diode (cathode to VIN, anode to VOUT) is mandatory for applications where VOUT may rise above VIN - such as hot-swap or backup power scenarios - to protect LP5952TLX-1.3/NOPB and upstream circuitry.
How does the EN pin behavior affect system power sequencing for LP5952TLX-1.3/NOPB?
The EN pin of LP5952TLX-1.3/NOPB is active-high with VIH ≥1 V and VIL ≤0.4 V. When pulled low, LP5952TLX-1.3/NOPB enters shutdown, drawing only 0.1 µA from VBATT. To avoid floating states, TI mandates tying EN to VBATT if unused. During power-up, EN must be asserted only after both VBATT and VIN are stable - incorrect sequencing (e.g., EN high before VBATT reaches 2.5 V) may cause erratic startup or increased inrush in LP5952TLX-1.3/NOPB.
LP5952TLX-1.3/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 5-WFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Output Configuration:
- Positive
- Output Type:
- Fixed
- Number of Regulators:
- 1
- Voltage - Input (Max):
- 4.5V
- Voltage - Output (Min/Fixed):
- 1.3V
- Voltage - Output (Max):
- -
- Voltage Dropout (Max):
- 0.2V @ 350mA
- Current - Output:
- 350mA
- Current - Quiescent (Iq):
- 28 µA
- Current - Supply (Max):
- 100 µA
- PSRR:
- 80dB ~ 64dB (10Hz ~ 100kHz)
- Control Features:
- Enable
- Protection Features:
- Over Current, Over Temperature, Short Circuit, Under Voltage Lockout (UVLO)
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 5-DSBGA (1.41x1.08)
LP5952TLX-1.3/NOPB FAQ
1.How can I place an order for LP5952TLX-1.3/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP5952TLX-1.3/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP5952TLX-1.3/NOPB reliable?
The price and inventory of LP5952TLX-1.3/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP5952TLX-1.3/NOPB is usually 5 days.
3.What payment methods are accepted for LP5952TLX-1.3/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP5952TLX-1.3/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP5952TLX-1.3/NOPB?
LP5952TLX-1.3/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP5952TLX-1.3/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP5952TLX-1.3/NOPB?
For technical support, including LP5952TLX-1.3/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP5952TLX-1.3/NOPB requirements.
6.How does Aetrix verify that LP5952TLX-1.3/NOPB is sourced from the original manufacturer or authorized distributors?
All LP5952TLX-1.3/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP5952TLX-1.3/NOPB meets industry standards.
7.What is the process for return or replacement of LP5952TLX-1.3/NOPB?
All LP5952TLX-1.3/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP5952TLX-1.3/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP5952TLX-1.3/NOPB part is unused and in its original packaging.
Return procedure for LP5952TLX-1.3/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LP5952TLX-1.3/NOPB Tags

-
MIC5504-1.8YM5-TR
Microchip Technology

-
MIC5504-3.3YM5-TR
Microchip Technology

-
MIC5365-3.0YC5-TR
Microchip Technology

-
MIC5365-1.8YC5-TR
Microchip Technology

-
MIC5365-2.5YC5-TR
Microchip Technology

-
MIC5365-3.3YC5-TR
Microchip Technology

-
MIC5365-3.3YD5-TR
Microchip Technology

-
MIC5317-3.3YM5-TR
Microchip Technology

-
TLV1117LV33DCYR
Texas Instruments

-
MIC5317-3.3YMT-TZ
Microchip Technology

-
MIC5528-3.3YMT-TR
Microchip Technology

-
TLV75801PDRVR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

