Texas Instruments LP8720TLE-B/NOPB
- Part No.:
- LP8720TLE-B/NOPB
- Manufacturer:
- Texas Instruments
- Category:
- Voltage Regulators - Linear + Switching
- Package:
- 20-WFBGA, DSBGA
- Datasheet:
-
LP8720TLE-B/NOPB.pdf
- Description:
- IC REG 6OUT BUCK/LNR SYNC 20USMD
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LP8720TLE-B/NOPB from Texas Instruments is a programmable power management IC integrating one 400 mA synchronous buck converter with dynamic voltage scaling (DVS) and five low-noise LDO regulators (LDO1–LDO5), each rated for up to 300 mA output. It features I²C-compatible serial interface, programmable power-on sequencing, thermal shutdown, and operates from 2.7 V to 4.5 V input. It is used in cellular handsets and portable handheld products requiring multi-rail, low-noise, and dynamically scalable power.
For engineers reviewing the LP8720TLE-B/NOPB datasheet, LP8720TLE-B/NOPB pinout, LP8720TLE-B/NOPB application, or LP8720TLE-B/NOPB equivalent, this page delivers verified technical context, exact pin functions, real-world use cases, and validated alternative parts - all grounded in TI's SNVS575B datasheet and official product documentation.
Technical Context
The LP8720TLE-B/NOPB implements a 2 MHz internal oscillator driving both the buck converter and control logic. Its buck stage supports automatic PFM/PWM mode switching, 1.9–2.1 MHz switching frequency, and external resistor feedback for output voltage programming (0.8 V–2.3 V). DVS enables runtime selection between two preconfigured buck voltages via dedicated pin or I²C register.
Each LDO features low dropout (200 mV typ @300 mA), ±2% output voltage accuracy, high PSRR, and independent enable/control via I²C. Startup sequencing is configurable through DEFSEL pin states (VBATT/GND/Hi-Z), defining default voltages and timing order across seven registers. Thermal protection includes early warning (125°C) and emergency shutdown (160°C), signaled via open-drain IRQ_N.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Buck Output Current | 400 mA max - supports core voltage rails for application processors in portable devices. |
| LDO Output Current (each) | 300 mA max - sufficient for analog sensors, RF ICs, and digital subsystems requiring low-noise bias. |
| Buck Output Voltage Range | 0.8 V to 2.3 V - programmable via I²C or external resistor divider for dynamic voltage scaling. |
| LDO Dropout Voltage | 200 mV typ @300 mA - enables operation with tight input-output margins in battery-powered systems. |
| I²C Interface Speed | 400 kHz - compatible with standard-mode I²C controllers for host-based configuration and monitoring. |
| Thermal Shutdown Threshold | 160°C - protects against sustained overtemperature during high-load or poor PCB thermal design. |
| Package | 20-bump DSBGA, 2.5 mm × 2.0 mm - ultra-compact footprint optimized for space-constrained mobile PCB layouts. |
Pinout & Package
LP8720TLE-B/NOPB uses a 20-bump, 0.4 mm pitch, 2.5 mm × 2.0 mm DSBGA package (TI package code YZR002011A) with bottom-side solder balls. Thermal pad is not present; thermal dissipation relies on PCB copper area under the package.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A4 VBATT | Power Input | Battery supply for LDO1 and internal circuitry; must be ≥2.7 V and ≤4.5 V. |
| E4 VINB | Power Input | Dedicated battery input for buck converter; decoupled with 10 µF ceramic capacitor. |
| A2 VIN1 | Power Input | Input for LDO2 and LDO3; requires 2.2 µF local decoupling. |
| D1 VIN2 | Power Input | Input for LDO4 and LDO5; shares same voltage domain as VIN1 but separate decoupling. |
| B4 LDO1 | Analog Output | Regulated output (1.2–3.3 V, 300 mA); used for noise-sensitive analog blocks like audio codecs. |
| A3 LDO2 | Analog Output | Regulated output (0.8–2.3 V, 300 mA); commonly configured for memory I/O or interface rails. |
| A1 LDO3 | Analog Output | Regulated output (0.8–2.85 V, 300 mA); default 1.8 V when DEFSEL = VBATT or Hi-Z. |
| C1 LDO4 | Analog Output | Regulated output (0.8–2.85 V, 300 mA); supports low-voltage peripherals such as SDIO or USB PHY. |
| E1 LDO5 | Analog Output | Regulated output (1.2–3.3 V, 300 mA); typically disabled at startup unless enabled via I²C. |
| E3 SW | Analog Output | Buck switch node; connects to external 2.2 µH inductor and 10 µF output capacitor. |
| D2 FB | Analog Input | Feedback input for buck regulator; sets output voltage via external resistor divider (VFB = 0.5 V). |
| D4 GNDB | Ground | Power ground for buck stage - must be routed separately from digital GND to minimize noise coupling. |
| B1 GND | Ground | Main IC ground reference for LDOs, logic, and I²C interface. |
| C4 SDA | Digital I/O | I²C data line; open-drain, requires 1.5 kΩ pull-up to VBATT or system IOVDD. |
| C3 SCL | Digital Input | I²C clock input; open-drain compatible, requires 1.5 kΩ pull-up. |
| B3 IRQ_N | Digital Output | Active-low interrupt output; signals thermal early warning or shutdown; requires 10 kΩ pull-up. |
| E2 EN | Digital Input | Enable control; high = active, low = standby; internal 500 kΩ pull-down ensures safe default state. |
| B2 DEFSEL | Digital Input | Defines startup sequence and default voltages: VBATT = setup 1, GND = setup 2, Hi-Z = setup 3. |
| C2 IDSEL | Digital Input | Sets I²C slave address: VBATT = 0x7F, Hi-Z = 0x7C, GND = 0x7D. |
| D3 DVS | Digital Input | Selects between two buck voltage sets (BUCK_V1/BUCK_V2); high = V1, low = V2. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable Power-On Sequencing | Startup order and delay per rail defined by DEFSEL state and register settings - eliminates need for external sequencers in multi-rail systems. |
| Dynamic Voltage Scaling (DVS) | Hardware-selectable dual buck voltage sets enable real-time processor voltage adaptation - reduces dynamic power without software overhead. |
| Low-Noise LDO Architecture | High PSRR (>60 dB @100 kHz) and <10 µVrms output noise support sensitive RF/analog circuits without additional filtering. |
| Ultra-Low Standby Current | 0.7 µA typical IQ in STANDBY mode - extends battery life during idle periods in always-on portable devices. |
| Integrated Thermal Protection | Two-stage thermal response (125°C warning + 160°C shutdown) with IRQ_N assertion and register-flag visibility - enables graceful system-level thermal management. |
| Configurable Sleep Mode | Reduces total quiescent current to ~100 µA when only LDO3 is active - ideal for sensor wake-up or low-power monitoring states. |
Applications
| Cellular Handset Baseband | Portable Media Player SoC |
|---|---|
Use Scenario: Powering application processor cores, memory interfaces, and baseband modem in GSM/UMTS smartphones. IC Role / Device Role / Timing Role: Central PMU providing DVS-controlled buck for CPU core and five independently sequenced LDOs for I/O, analog, and RF subsystems. Use Value: Enables adaptive voltage/frequency scaling per workload while maintaining strict noise isolation between digital and RF domains. |
Use Scenario: Supplying multiple voltage domains in portable media players with LCD, audio DAC, flash memory, and touch controller. IC Role / Device Role / Timing Role: Single-chip power source delivering 1.2 V (core), 1.8 V (memory), 2.8 V (LCD bias), 3.3 V (USB PHY), and 1.0 V (audio codec) with controlled ramp timing. Use Value: Eliminates discrete regulators and sequencing ICs - reduces BOM count, PCB area, and layout complexity in compact form factors. |
| Wireless Handheld Scanner | Industrial Handheld Terminal |
Use Scenario: Powering CMOS image sensor, laser driver, Bluetooth radio, and microcontroller in barcode scanners. IC Role / Device Role / Timing Role: LDO2 (1.8 V) powers sensor analog front-end; LDO4 (2.8 V) drives laser diode; buck supplies MCU core at 1.2 V with DVS during decode bursts. Use Value: Low-noise LDO outputs prevent image artifacts; buck efficiency extends battery runtime during intermittent high-current scanning. |
Use Scenario: Supporting ruggedized terminals with display, keypad, RFID reader, and 802.11/Wi-Fi module operating in extended temperature range. IC Role / Device Role / Timing Role: LDO1 (3.0 V) powers Wi-Fi transceiver; LDO3 (1.8 V) supplies FPGA I/O; buck (1.2 V) feeds ARM Cortex-M7 core with thermal-aware throttling. Use Value: Thermal shutdown and early warning flags allow firmware to reduce CPU load before critical overheating - improves field reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-rail power management applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS65023RSBR | Three buck converters + six LDOs; no DVS; 2.25–6.5 V input; larger 48-pin QFN package. | Higher integration for complex SoCs; lacks hardware DVS pin - requires I²C writes for voltage changes. | Choose for designs needing >1 buck rail or wider input range; avoid if board space or DVS latency are constraints. |
| LP87322ARHPT | Two bucks + four LDOs; I²C + GPIO control; 2.5–5.5 V input; 24-pin VQFN; integrated watchdog and reset generator. | Includes system-level supervision features absent in LP8720TLE-B/NOPB; no dedicated DVS pin but supports dynamic voltage change via I²C. | Prefer when system-level reset management and dual-buck flexibility outweigh need for hardware DVS and minimal footprint. |
Compared with TPS65023RSBR and LP87322ARHPT, the LP8720TLE-B/NOPB offers the smallest package (2.5×2.0 mm), lowest standby current (0.7 µA), and fastest hardware-triggered DVS response - making it optimal for ultra-compact, battery-sensitive handhelds where single-buck + five-LDO architecture suffices.
Availability
LP8720TLE-B/NOPB is available at Aetrix Electronics and suitable for cellular handsets, portable media players, wireless handheld scanners, and industrial handheld terminals requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for LP8720TLE-B/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with decades of experience in mobile and portable power solutions.
The LP8720TLE-B/NOPB belongs to TI's low-power, multi-rail PMU product line designed specifically for space-constrained, battery-operated handheld devices requiring high integration, low noise, and intelligent power sequencing.
FAQ
What is the maximum supported input voltage for LP8720TLE-B/NOPB?
The absolute maximum input voltage on VBATT, VINB, VIN1, and VIN2 pins is 6 V, but the recommended operating range is 2.7 V to 4.5 V per TI's SNVS575B datasheet. Exceeding 4.5 V risks violating operating ratings and may trigger overvoltage protection or damage. The LP8720TLE-B/NOPB is optimized for single-cell Li-ion/Li-poly battery systems, and operation outside 2.7–4.5 V is not characterized or guaranteed.
Does LP8720TLE-B/NOPB support hardware-based dynamic voltage scaling?
Yes, LP8720TLE-B/NOPB supports hardware-based DVS via the DVS pin (Pin D3). When EXT_DVS_CONTROL bit in Register 0x00 is set to 1, asserting DVS = HI selects BUCK_V1 and DVS = LO selects BUCK_V2 - enabling sub-microsecond voltage transitions without I²C traffic. This feature is explicitly documented in Tables 4 and 5 of the SNVS575B datasheet and is a key differentiator versus software-only alternatives.
How many LDO outputs does LP8720TLE-B/NOPB provide, and what are their current ratings?
LP8720TLE-B/NOPB provides five independent LDO outputs: LDO1 through LDO5. Each is rated for up to 300 mA continuous output current, with typical dropout voltage of 200 mV at full load. LDO1–LDO4 support output ranges from 0.8 V to 3.3 V; LDO5 is fixed at 1.2–3.3 V. All LDOs maintain ±2% output voltage accuracy across load, line, and temperature per the Electrical Characteristics table.
What package type and dimensions does LP8720TLE-B/NOPB use?
LP8720TLE-B/NOPB uses a 20-bump DSBGA (Die Size Ball Grid Array) package with mechanical dimensions of 2.5 mm × 2.0 mm and 0.4 mm ball pitch. TI's official package drawing (YZR002011A) confirms this footprint. No thermal pad is included; thermal performance relies on PCB copper area under the package and proper solder joint formation per IPC-7095 guidelines.
Can LP8720TLE-B/NOPB operate without an external I²C host controller?
Yes, LP8720TLE-B/NOPB can operate without continuous I²C communication. Default voltages and startup sequences are determined by DEFSEL and IDSEL pin states at power-on reset. Once configured, LDOs and buck remain active in IDLE mode without host intervention. I²C is required only for dynamic reconfiguration (e.g., changing voltages, enabling/disabling rails, reading status registers), not for basic functionality.
LP8720TLE-B/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 20-WFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Topology:
- Step-Down (Buck) Synchronous (1), Linear (LDO) (5)
- Number of Outputs:
- 6
- Frequency - Switching:
- 2MHz
- Voltage/Current - Output 1:
- 0.8V ~ 2.3V, 400mA
- Voltage/Current - Output 2:
- 1.2V ~ 3.3V, 300mA
- Voltage/Current - Output 3:
- 1.2V ~ 3.3V, 300mA
- w/LED Driver:
- No
- w/Supervisor:
- No
- w/Sequencer:
- Yes
- Voltage - Supply:
- 2.7V ~ 4.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-DSBGA
LP8720TLE-B/NOPB FAQ
1.How can I place an order for LP8720TLE-B/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP8720TLE-B/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP8720TLE-B/NOPB reliable?
The price and inventory of LP8720TLE-B/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP8720TLE-B/NOPB is usually 5 days.
3.What payment methods are accepted for LP8720TLE-B/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP8720TLE-B/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP8720TLE-B/NOPB?
LP8720TLE-B/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP8720TLE-B/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP8720TLE-B/NOPB?
For technical support, including LP8720TLE-B/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP8720TLE-B/NOPB requirements.
6.How does Aetrix verify that LP8720TLE-B/NOPB is sourced from the original manufacturer or authorized distributors?
All LP8720TLE-B/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP8720TLE-B/NOPB meets industry standards.
7.What is the process for return or replacement of LP8720TLE-B/NOPB?
All LP8720TLE-B/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP8720TLE-B/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP8720TLE-B/NOPB part is unused and in its original packaging.
Return procedure for LP8720TLE-B/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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