Texas Instruments LP8731QYZRRQ1

Overview

LP8731QYZRRQ1 from Texas Instruments is an automotive-grade dual-buck + dual-LDO power management IC for ADAS domain controllers, delivering 1.2-A buck outputs at 0.8875–1.675 V and 300-mA LDOs at 0.8–3.3 V with ±2% buck / ±3% LDO accuracy, I²C programmability, and AEC-Q100 Grade-1 qualification.

For engineers reviewing the LP8731QYZRRQ1 datasheet, LP8731QYZRRQ1 pinout, LP8731QYZRRQ1 application, or LP8731QYZRRQ1 equivalent, key selection considerations include factory-default sequencing (Buck1→Buck2→LDO1→LDO2), thermal shutdown at 160°C, 2.1-MHz PWM switching, 400-kHz I²C interface timing, and DSBGA-25 (2.52 mm × 2.52 mm) packaging for space-constrained automotive modules.

Technical Context

The LP8731QYZRRQ1 integrates two synchronous step-down converters (SW1/SW2) using voltage-mode PWM control with input feedforward, enabling >90% efficiency and ±2% output accuracy across 0.8875–1.675 V. Each buck features 1.7-A peak current limiting, soft-start with stepped current ramping (180/300/720 mA), and 100% duty-cycle low-dropout operation down to VIN = VOUT + ILOAD×(RDSON,P + RIND).

Two identical PMOS-based LDOs (LDO1/LDO2) provide low-noise analog supply with 30-mV typical dropout at 250 mA, ±3% accuracy, and 280 µVrms integrated output noise (10 Hz–100 kHz). All regulators support independent enable via dedicated pins (ENSW1/ENSW2/ENLDO1/ENLDO2) or I²C register control, with flexible sequencing triggered by rising-edge EN_T assertion.

Key Specifications

Pinout & Package

LP8731QYZRRQ1 uses a 25-pin DSBGA (YZR) package with 0.4-mm pitch, optimized for thermal performance in automotive under-hood environments. The package includes dedicated ground planes (GND_L, GND_SW1, GND_SW2, GND_C) and separate power domains (VINLDO12, AVDD, VIN1/VIN2) to minimize noise coupling between analog and switching sections.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar multi-rail power management applications.

Compared with TPS65917Q1RSLRQ1 and LP87524BRSNRQ1, the LP8731QYZRRQ1 uniquely balances dual-buck + dual-LDO integration, 25-pin DSBGA compactness, and hardware sequencing (EN_T/nPOR) - making it optimal for ADAS domain controllers needing both digital and analog rail coordination in constrained spaces.

Availability

LP8731QYZRRQ1 is available at Aetrix Electronics and suitable for advanced driver assistance systems (ADAS), automotive camera modules, and radar signal processing units requiring stable component supply with AEC-Q100 compliance and long-term automotive lifecycle support.

Supply support for LP8731QYZRRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive electronics, with decades of experience in power management innovation.

The LP8731QYZRRQ1 belongs to TI's automotive-qualified power management unit (PMU) product line, designed specifically for ADAS domain controllers requiring tightly coordinated multi-rail power delivery with programmable sequencing and high reliability under harsh environmental conditions.

FAQ

What is the default output voltage configuration for LP8731QYZRRQ1?

The LP8731QYZRRQ1 ships with factory-programmed default voltages: Buck1 and Buck2 at 1.0625 V, LDO1 at 2.8 V, and LDO2 at 3.3 V. These values are stored in one-time-programmable memory and can be modified via I²C registers during system initialization. The I²C address defaults to 0x59, and all regulators are enabled by default after power-on unless overridden by external enable pins.

How does the EN_T pin control power sequencing on LP8731QYZRRQ1?

The EN_T pin on LP8731QYZRRQ1 is a rising-edge-triggered input that initiates the device's preset power-on sequence: Buck1 activates after 1.5 ms, followed by Buck2 at 2 ms, LDO1 at 3 ms, and LDO2 at 6 ms. A falling edge on EN_T starts shutdown in reverse order. During EN_T assertion, external enable pins (ENSW1/ENSW2/ENLDO1/ENLDO2) are ignored, ensuring deterministic sequencing without software intervention.

What thermal protection mechanisms does LP8731QYZRRQ1 implement?

The LP8731QYZRRQ1 incorporates thermal shutdown at 160°C junction temperature with 20°C hysteresis, preventing permanent damage during sustained overload. It also features current limiting (1.7-A peak per buck) and undervoltage lockout (2.7-V falling threshold) to avoid operation outside safe electrical boundaries. The DSBGA-25 package achieves 58.7°C/W junction-to-ambient thermal resistance, supporting continuous 1.2-A operation at 125°C ambient when properly mounted on a 4-layer PCB with thermal vias.

Can LP8731QYZRRQ1 operate with input voltages below 2.8 V?

The LP8731QYZRRQ1 Buck converters require a minimum 2.8-V input (VIN1/VIN2) per recommended operating conditions, but the LDOs can function down to 2.45 V on their respective inputs (VINLDO1/VINLDO2) when enabled. Below 2.8 V, the bucks enter dropout mode with reduced efficiency and increased ripple; operation below 2.45 V disables LDO regulation entirely. For cold-cranking scenarios, the UVLO circuit holds all regulators off until VIN exceeds 2.7 V to ensure clean startup.

What is the purpose of the nPOR pin on LP8731QYZRRQ1?

The nPOR pin on LP8731QYZRRQ1 is an open-drain power-good indicator signaling valid output voltage on both Buck1 and Buck2. It remains low until each buck reaches 94% of its target voltage during power-up and asserts high after a 50-µs delay. During faults (UVLO, thermal shutdown, or output undervoltage), nPOR pulls low to notify the host processor. A 100-kΩ external pull-up resistor is required, and the pin shares no relationship with the internal LDO power-good signals.