Texas Instruments LP8755KME/NOPB
- Part No.:
- LP8755KME/NOPB
- Manufacturer:
- Texas Instruments
- Package:
- 49-WFBGA, DSBGA
- Datasheet:
-
LP8755KME/NOPB.pdf
- Description:
- IC REG BUCK PROG 15A HEX 49DSBGA
- Quantity:
- Payment:

- Shipping:

Inventory:1,205
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LP8755KME/NOPB from Texas Instruments is a six-phase, multi-core step-down DC-DC converter IC designed for high-efficiency power delivery to application processors in mobile devices. It delivers up to 15 A total output current across six bundled buck cores, supports 0.6 V to 1.67 V programmable output voltage, operates at up to 4 MHz switching frequency, and integrates remote differential voltage sensing for precise point-of-load regulation in smartphones and tablets.
For engineers reviewing the LP8755KME/NOPB datasheet, LP8755KME/NOPB pinout, LP8755KME/NOPB application, or LP8755KME/NOPB equivalent, key selection considerations include phase-add/shed thresholds (300–1000 mA), load-current reporting capability, I²C-compatible interface with four address options, and thermal warning flag support for system-level power management.
Technical Context
The LP8755KME/NOPB implements a fully synchronous, current-mode controlled 6-phase buck architecture with automatic phase adding/shedding and dual-mode operation (PWM/PFM). Each core features integrated high-side and low-side MOSFETs with typical RDS(ON) of 60 mΩ (PFET) and 50 mΩ (NFET), enabling high efficiency across 0.5 mA to 15 A load range.
It uses SmartReflex™-compatible DVS control via dedicated SR interface or standard I²C (100/400 kHz/3.4 MHz), supports programmable overcurrent protection per core (2.7–3.7 A high-side limit), and includes remote feedback pins (FBB0+/B0 and FBB0−/B1) for IR-drop compensation - critical for sub-1V processor core rails.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Output Current | 15 A total (six phases combined); enables single-rail high-current CPU/GPU core supply without external parallel controllers. |
| Output Voltage Range | 0.6 V to 1.67 V in 10-mV steps; supports dynamic voltage scaling for ARM Cortex-A series and similar application processors. |
| Switching Frequency | Up to 4.5 MHz (typ. 4 MHz at VOUT ≥ 0.8 V); allows use of ultra-small 0.25–1 µH inductors and compact 30–50 µF ceramic output capacitance. |
| Efficiency Peak | ≥90% at 1–5 A load (VIN = 3.8 V); achieved via adaptive phase shedding and auto PWM/PFM mode transition. |
| Remote Sensing | Differential feedback (FBB0+/B0 & FBB0−/B1); compensates PCB trace IR drop to maintain ±0.5% output accuracy at point-of-load. |
| I²C Interface | Supports Standard (100 kHz), Fast (400 kHz), and High-Speed (3.4 MHz) modes; four selectable addresses (60h–63h) enable multi-device bus sharing. |
| Thermal Protection | Two-stage OTP warning (first at 105°C, second at 120°C); triggers interrupt and enables host-controlled throttling before 125°C junction limit. |
Pinout & Package
LP8755KME/NOPB is housed in a 49-pin DSBGA (YFQ) package measuring 3.022 mm × 2.882 mm with 0.4-mm pitch. The package features an exposed thermal pad on the bottom for enhanced PCB heat dissipation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VINB0/B1, VINB2, VINB3/B4, VINB5 | Input power supply for respective buck cores | Separate VIN pins per core group must be externally tied together and locally bypassed; enables flexible layout and reduced input ripple coupling. |
| SWB0–SWB5 | Switch node outputs | Direct connection points to external inductors; each SW pin drives one buck phase; requires low-inductance routing to minimize EMI. |
| FBB0+/B0 & FBB0−/B1 | Remote differential feedback inputs | Connect to processor VDD/VSS sense pads; enables accurate regulation despite PCB voltage drop between IC and SoC. |
| SDASYS / SCLSYS | I²C system interface | Standard bidirectional data/clock lines; require external 10-kΩ pullups to VIOSYS; support full register read/write including per-core current monitoring. |
| NRST | Reset input | Active-HIGH start-up trigger; initiates soft-start sequence and output voltage ramp; internal POR ensures reliable initialization. |
| INT | Open-drain interrupt output | Signals fault conditions (OCP, OTP, UVLO) or status events (phase add/shed, thermal warning); programmable mask register disables non-critical alerts. |
Key Features
| Feature | Design Value |
|---|---|
| Automatic phase adding/shedding | Configurable thresholds (300–1000 mA add, 300–900 mA shed) dynamically optimize efficiency across 0.5 mA–15 A load range. |
| Load current reporting | I²C-readable total load current and per-core current values - eliminates need for external current-sense resistors or amplifiers. |
| Programmable output ramp rate | 8-step adjustable slew rate (0.23–30 mV/µs) prevents overshoot during startup and enables controlled power sequencing. |
| Spread spectrum & phase control | Reduces peak EMI by dithering switching frequency and offsetting phase timing - simplifies compliance with FCC/CE radiated emission limits. |
| SmartReflex™-compatible DVS interface | Dedicated SDASR/SCLSR pins allow independent voltage scaling control from baseband processor, decoupling power management from main I²C bus. |
Applications
| Smartphone Application Processor Supply | eBook/Tablet SoC Core Rail |
|---|---|
|
Use Scenario: Powering ARM-based application processors (e.g., Qualcomm Snapdragon, MediaTek MT series) requiring dynamic voltage scaling and tight transient response. IC Role / Device Role / Timing Role: Primary 6-phase buck regulator delivering core voltage (VDD_CPU) with remote sensing and real-time load-current telemetry. Use Value: Maintains ±15 mV transient deviation under 400-ns 0.6 A → 2 A load steps while enabling software-controlled DVFS via I²C or DVS interface. |
Use Scenario: Supplying multi-core SoCs in 7–10 inch tablets where board space is constrained but thermal headroom is limited. IC Role / Device Role / Timing Role: Single-chip, high-density 15-A power solution replacing discrete multi-phase controllers and reducing BOM count by >40%. Use Value: 4-MHz operation allows use of 0.47-µH inductors and 33-µF MLCCs, shrinking total solution size by ~35% versus 2-MHz alternatives. |
| Gaming Handheld System-on-Chip | LTE/5G Mobile Baseband Power |
|
Use Scenario: Supporting burst-mode workloads in portable gaming devices with rapid CPU/GPU clock scaling and thermal throttling requirements. IC Role / Device Role / Timing Role: Adaptive 6-phase regulator with dual OTP warning flags and interrupt-driven thermal management for runtime power budgeting. Use Value: Phase shedding below 300 mA and forced-PWM above 1 A ensure >85% efficiency across 100 µA–10 A, extending battery life during mixed-use scenarios. |
Use Scenario: Delivering stable, low-noise power to LTE/5G baseband processors (e.g., Intel XMM, Qualcomm MDM) with stringent ripple and EMI requirements. IC Role / Device Role / Timing Role: Low-ripple, spread-spectrum-enabled buck controller meeting 3GPP RF coexistence specifications for cellular front-end modules. Use Value: <7 mVPP PWM ripple (200 mA load) and programmable phase offsets suppress narrowband EMI peaks, easing RF module integration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar multi-phase buck converter applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TPS659122YFFR | 4-phase, 12-A max; lacks remote sensing; fixed 0.7–1.52 V output range; no per-core current reporting. | Targeted at lower-power application processors; suitable when thermal margin exceeds 20°C and point-of-load accuracy < ±1% is acceptable. | Select if system uses simpler I²C-only control and does not require SmartReflex™ DVS interface or differential feedback. |
| RTQ2134BGQW | 6-phase, 16-A max; supports 0.3–1.8 V output; includes PMBus interface; higher RDS(ON) (85 mΩ PFET); no built-in thermal warning flags. | Designed for industrial embedded systems with longer qualification cycles; requires external temperature monitoring for safe high-current operation. | Prefer when PMBus compatibility, wider VOUT range, or extended temperature rating (–40°C to +125°C) outweighs loss of integrated thermal alerting. |
Compared with TPS659122YFFR and RTQ2134BGQW, the LP8755KME/NOPB uniquely combines remote differential sensing, per-core current telemetry, and dual-stage thermal warning in a 3-mm DSBGA - making it the only option among the three qualified for high-accuracy, thermally constrained smartphone SoC core rail designs.
Availability
LP8755KME/NOPB is available at Aetrix Electronics and suitable for smartphone power management, tablet SoC core supply, and LTE/5G baseband applications requiring stable component supply, long-term lifecycle support, and automotive-grade reliability screening.
Supply support for LP8755KME/NOPB includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and power management technologies, with over 50 years of innovation in high-efficiency DC-DC conversion.
The LP8755KME/NOPB belongs to TI's LP87xx family of SmartReflex™-enabled multi-phase power management ICs, engineered specifically for dynamic voltage scaling and thermal-aware power delivery in advanced mobile application processors.
FAQ
What is the maximum continuous output current supported by the LP8755KME/NOPB?
The LP8755KME/NOPB supports up to 15 A total output current when all six phases operate in parallel under proper thermal conditions. This rating assumes adequate PCB copper area, thermal vias to inner layers, and ambient temperature ≤85°C. At 125°C junction limit, sustained current may be thermally limited below 15 A depending on layout and airflow.
Does the LP8755KME/NOPB require external current-sense resistors for load monitoring?
No, the LP8755KME/NOPB does not require external current-sense resistors. It integrates MOSFET RDS(ON)-based current sensing per buck core and provides real-time total load current and individual core current values via its I²C interface - enabling precise telemetry without added BOM cost or board space.
Can the LP8755KME/NOPB be used with a 2.8-V input supply?
Yes, the LP8755KME/NOPB supports input voltages from 2.5 V to 5 V per its recommended operating conditions. At 2.8 V input, the device maintains full functionality including 0.6–1.67 V output programmability, phase add/shed, and I²C communication - though maximum achievable output current decreases due to reduced headroom.
How does the LP8755KME/NOPB handle thermal overload conditions?
The LP8755KME/NOPB implements two-stage thermal protection: a first warning flag triggers at 105°C junction temperature, and a second critical flag activates at 120°C. Both generate interrupts on the INT pin. If the second flag occurs, the host system must reduce load current immediately to prevent shutdown at 125°C - ensuring graceful thermal management without abrupt failure.
Is remote differential voltage sensing mandatory for LP8755KME/NOPB operation?
No, remote differential sensing is optional. The LP8755KME/NOPB can operate in local feedback mode using internal reference, but doing so sacrifices point-of-load accuracy due to PCB trace IR drop. For sub-1V core rails where ±10 mV tolerance is required, connecting FBB0+/B0 and FBB0−/B1 to the processor's sense pads is strongly recommended.
LP8755KME/NOPB Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 49-WFBGA, DSBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Function:
- Step-Down
- Output Configuration:
- Positive
- Topology:
- Buck
- Output Type:
- Programmable
- Number of Outputs:
- 6
- Voltage - Input (Min):
- 2.5V
- Voltage - Input (Max):
- 5V
- Voltage - Output (Min/Fixed):
- 0.6V
- Voltage - Output (Max):
- 1.67V
- Current - Output:
- 15A
- Frequency - Switching:
- 4MHz
- Synchronous Rectifier:
- Yes
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 49-DSBGA
LP8755KME/NOPB FAQ
1.How can I place an order for LP8755KME/NOPB through Aetrix?
Please submit a Request for Quotation (RFQ) for LP8755KME/NOPB on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LP8755KME/NOPB reliable?
The price and inventory of LP8755KME/NOPB are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LP8755KME/NOPB is usually 5 days.
3.What payment methods are accepted for LP8755KME/NOPB?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LP8755KME/NOPB transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LP8755KME/NOPB?
LP8755KME/NOPB orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LP8755KME/NOPB order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LP8755KME/NOPB?
For technical support, including LP8755KME/NOPB datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LP8755KME/NOPB requirements.
6.How does Aetrix verify that LP8755KME/NOPB is sourced from the original manufacturer or authorized distributors?
All LP8755KME/NOPB products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LP8755KME/NOPB meets industry standards.
7.What is the process for return or replacement of LP8755KME/NOPB?
All LP8755KME/NOPB units undergo pre-shipment inspection (PSI). If there is an issue with LP8755KME/NOPB, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LP8755KME/NOPB part is unused and in its original packaging.
Return procedure for LP8755KME/NOPB:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LP8755KME/NOPB Tags

-
TPS562201DDCR
Texas Instruments

-
MC34063ABD-TR
STMicroelectronics

-
TPS561201DDCR
Texas Instruments

-
MC33063ADR
Texas Instruments

-
MC34063ADR
Texas Instruments
-
TPS560200DBVR
Texas Instruments

-
AP3012KTR-G1
Diodes Incorporated

-
TLV61048DBVR
Texas Instruments

-
AZ34063UMTR-G1
Diodes Incorporated

-
TPS562200DDCR
Texas Instruments

-
AP62300TWU-7
Diodes Incorporated

-
MC34063EBD-TR
STMicroelectronics
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

.jpg)