NXP Semiconductors LPC1111FHN33/102,5
- Part No.:
- LPC1111FHN33/102,5
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 32-VQFN Exposed Pad
- Datasheet:
-
LPC1111FHN33/102,5.pdf
- Description:
- IC MCU 32BIT 8KB FLASH 32HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,953
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC1111FHN33/102 from NXP Semiconductors is an ARM Cortex-M0 32-bit microcontroller in HVQFN33 package, featuring 8 kB flash, 2 kB SRAM, 28 GPIO pins, one UART with RS-485 support, one I²C-bus interface (Fast-mode Plus), and a 10-bit ADC with 8 input channels - deployed in lighting control and alarm system firmware.
For engineers reviewing the LPC1111FHN33/102 datasheet, LPC1111FHN33/102 pinout, LPC1111FHN33/102 application, or LPC1111FHN33/102 equivalent, this page delivers verified technical context, package-specific pin roles, power profile capabilities, and validated alternative options for industrial embedded design.
Technical Context
The LPC1111FHN33/102 implements the ARM Cortex-M0 core with Nested Vectored Interrupt Controller (NVIC) and operates at up to 50 MHz CPU frequency using internal RC oscillator (1 % trimmed) or external crystal (1–25 MHz). It integrates a programmable windowed watchdog timer and supports Sleep, Deep-sleep, and Deep power-down modes via its on-chip PMU.
Digital peripherals include four general-purpose timers (two 32-bit, two 16-bit), edge/level-sensitive GPIO interrupts, and configurable open-drain mode on all GPIOs. Analog functionality centers on an 8-channel 10-bit ADC with multiplexed inputs, while serial interfaces comprise one UART with fractional baud rate generation and FIFO, one Fast-mode Plus I²C-bus (1 Mbit/s), and one SPI controller with SSP features.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0, 32-bit RISC architecture optimized for deterministic real-time response in resource-constrained systems. |
| Max Clock Frequency | 50 MHz - enables high-throughput sensor polling and fast interrupt handling without external clocking complexity. |
| Flash Memory | 8 kB - sufficient for compact firmware with bootloader, communication stack, and application logic in cost-sensitive devices. |
| SRAM | 2 kB - supports moderate variable storage, stack depth, and small data buffers for UART/I²C message handling. |
| GPIO Count | 28 pins - provides scalable digital I/O for LED drivers, button inputs, relay controls, and peripheral expansion in HVQFN33 footprint. |
| ADC Resolution & Channels | 10-bit with 8 multiplexed inputs - delivers adequate precision for temperature, light, and voltage monitoring in white goods and metering. |
| I²C Speed Mode | Fast-mode Plus (1 Mbit/s) - allows high-speed communication with multiple sensors or displays while maintaining noise immunity. |
| Power Profiles | Enabled - permits runtime selection of performance/power trade-offs via single function call in boot ROM. |
Pinout & Package
HVQFN33 package: plastic thermal enhanced very thin quad flat package, no leads, 33 terminals, body size 7 × 7 × 0.85 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RESET/PIO0_0 | Reset input / General-purpose I/O | Active-low hardware reset with configurable pull-up; dual-use as GPIO for status signaling or wake-up trigger. |
| XTALIN / XTALOUT | Clock oscillator inputs | Supports external crystal (1–25 MHz) for precise timing; internal 12 MHz RC oscillator available as fallback. |
| SWDIO / SWCLK | Serial Wire Debug interface | Enables non-intrusive debugging and programming via standard ARM SWD protocol without dedicated JTAG pins. |
| PIO0_4/SCL / PIO0_5/SDA | I²C-bus interface | Fast-mode Plus compliant (1 Mbit/s); supports multi-master arbitration and monitor mode for bus diagnostics. |
| PIO1_6/RXD / PIO1_7/TXD | UART channel | RS-485/EIA-485 compatible with fractional baud rate generator and internal FIFO for robust industrial comms. |
| PIO0_9/MOSI0 / PIO0_8/MISO0 / PIO0_6/SCK0 / PIO0_2/SSEL0 | SPI0 interface | Full-duplex synchronous serial interface supporting master/slave operation and SSP features including DMA-ready FIFO. |
| AD[7:0] | Analog-to-digital converter inputs | 8-channel 10-bit ADC with selectable reference; supports simultaneous sampling and burst conversion for sensor arrays. |
| VDD / VSS | Power supply terminals | Single 1.8–3.6 V supply; VSS terminal 33 provides ground reference for analog/digital domains and thermal pad connection. |
Key Features
| Feature | Design Value |
|---|---|
| Programmable windowed WDT | Prevents runaway code execution with time-window enforcement - critical for fail-safe operation in alarm systems. |
| Configurable open-drain GPIO | Enables direct interfacing with I²C buses, wired-AND logic, and level-shifting circuits without external components. |
| Power Management Unit (PMU) | Reduces active current to <100 µA in Deep-sleep mode with wake-up via 13 GPIOs - extends battery life in portable lighting. |
| High-current GPIO drivers | 20 mA sink capability on I²C pins supports direct LED driving or bus termination without external transistors. |
| In-Application Programming (IAP) | Allows firmware updates over UART or I²C without external programmer - simplifies field maintenance in eMetering deployments. |
Applications
| Lighting Control | Alarm System |
|---|---|
Use Scenario: Dimmable LED driver board with ambient light sensing and wireless command reception. IC Role / Device Role / Timing Role: Main system controller executing PWM generation, ADC-based lux measurement, and UART-based command parsing. Use Value: 28 GPIOs enable direct MOSFET gate drive and sensor interfacing; 8 kB flash accommodates lighting profiles and OTA update handler. | Use Scenario: Standalone intrusion detection panel with door/window contact inputs and siren output. IC Role / Device Role / Timing Role: Central security processor managing zone polling, tamper detection, and audible alert timing. Use Value: Windowed WDT ensures reliable fault recovery; Deep-sleep mode draws <100 µA during standby - extends backup battery life to >1 year. |
| eMetering | White Goods |
Use Scenario: Smart electricity meter with pulse counting, tariff switching, and optical port communication. IC Role / Device Role / Timing Role: Metering co-processor handling pulse accumulation, RTC synchronization, and I²C EEPROM access. Use Value: Fast-mode Plus I²C (1 Mbit/s) accelerates configuration read/write; 10-bit ADC measures auxiliary supply voltage with ±1 LSB accuracy. | Use Scenario: Washing machine main control board managing motor sequencing, water level sensing, and user interface. IC Role / Device Role / Timing Role: Primary MCU coordinating motor driver signals, thermistor readings, and display refresh via SPI. Use Value: 50 MHz Cortex-M0 core executes PID loops within 10 µs; 2 kB SRAM buffers sensor data across 16 concurrent tasks. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1111FHN33/202 | Same package and pinout; 4 kB SRAM instead of 2 kB; identical flash (8 kB) and peripheral set. | Better suited for applications requiring larger stack depth or buffer space for protocol stacks (e.g., Modbus RTU over UART). | Select when additional RAM is needed without changing PCB layout or firmware architecture. |
| LPC1112FHN33/102 | Same HVQFN33 package; 16 kB flash (vs. 8 kB); 2 kB SRAM; identical peripherals and clocking. | Preferred for designs anticipating firmware growth or needing dual-bank bootloading capability. | Choose when future feature expansion or field-upgrade resilience is required, with no change to pin compatibility. |
Compared with LPC1111FHN33/102, the /202 variant adds 2 kB SRAM for deeper buffering without altering flash or peripherals, while the /102 variant of LPC1112 doubles flash capacity for complex control algorithms - both retain identical HVQFN33 pinout and power profile support.
Availability
LPC1111FHN33/102 is available at Aetrix Electronics and suitable for lighting control, alarm systems, and eMetering applications requiring stable component supply, long-term lifecycle assurance, and industrial-grade temperature range (−40 °C to +85 °C).
Supply support for LPC1111FHN33/102 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC111x series targets cost-sensitive 8/16-bit replacement applications, delivering ARM Cortex-M0 performance with ultra-low power consumption, integrated analog peripherals, and simplified toolchain support for rapid embedded development.
FAQ
What is the maximum operating frequency of the LPC1111FHN33/102?
The LPC1111FHN33/102 operates at a maximum CPU frequency of 50 MHz. This speed is achievable using either the internal 12 MHz RC oscillator (trimmed to ±1 % accuracy) or an external crystal oscillator ranging from 1 MHz to 25 MHz, with optional PLL multiplication. The 50 MHz clock drives all peripherals synchronously, enabling deterministic real-time response in time-critical applications such as lighting dimming or alarm event processing.
Does the LPC1111FHN33/102 support In-Application Programming (IAP)?
Yes, the LPC1111FHN33/102 supports In-Application Programming via its on-chip bootloader. This allows firmware updates to be performed while the device is running - for example, over UART or I²C - without requiring an external programmer. The IAP functionality is accessible through documented API calls in the boot ROM, enabling secure and field-upgradable firmware in products like smart meters and alarm panels where physical access is limited.
What is the ADC resolution and channel count on the LPC1111FHN33/102?
The LPC1111FHN33/102 integrates a 10-bit successive approximation ADC with 8 multiplexed input channels (AD[7:0]). These channels are available on the HVQFN33 package and support programmable sample rates, burst mode, and selectable reference sources (VDD or internal bandgap). The ADC is commonly used for sensor signal acquisition in white goods and lighting systems, delivering ±1 LSB integral nonlinearity and monotonicity across its full range.
Is the LPC1111FHN33/102 pin-compatible with other LPC111x HVQFN33 variants?
Yes, the LPC1111FHN33/102 shares identical pinout and package dimensions (HVQFN33, 7 × 7 × 0.85 mm) with all other LPC111x family members in the same package variant, including LPC1111FHN33/101, /103, /201, /202, /203, and LPC1112FHN33/102. This enables drop-in replacement during prototyping or production ramp-up, provided firmware and power requirements align with the specific variant's flash, SRAM, and feature set.
What power-saving modes does the LPC1111FHN33/102 support?
The LPC1111FHN33/102 supports three reduced-power modes: Sleep, Deep-sleep, and Deep power-down. In Deep-sleep mode, current consumption drops below 100 µA while retaining SRAM and register contents, with wake-up possible via up to 13 GPIO pins or RTC alarm. Deep power-down reduces current to ~1 µA but requires full reset on wake-up. These modes are managed by the integrated Power Management Unit (PMU) and are activated via CMSIS-compliant APIs, making them ideal for battery-powered alarm sensors and portable lighting controllers.
LPC1111FHN33/102,5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VQFN Exposed Pad
- Series:
- LPC1100L
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 28
- Program Memory Size:
- 8KB (8K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 8x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1111FHN33/102,5 FAQ
1.How can I place an order for LPC1111FHN33/102,5 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1111FHN33/102,5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1111FHN33/102,5 reliable?
The price and inventory of LPC1111FHN33/102,5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1111FHN33/102,5 is usually 5 days.
3.What payment methods are accepted for LPC1111FHN33/102,5?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1111FHN33/102,5 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC1111FHN33/102,5?
LPC1111FHN33/102,5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1111FHN33/102,5 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1111FHN33/102,5?
For technical support, including LPC1111FHN33/102,5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1111FHN33/102,5 requirements.
6.How does Aetrix verify that LPC1111FHN33/102,5 is sourced from the original manufacturer or authorized distributors?
All LPC1111FHN33/102,5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1111FHN33/102,5 meets industry standards.
7.What is the process for return or replacement of LPC1111FHN33/102,5?
All LPC1111FHN33/102,5 units undergo pre-shipment inspection (PSI). If there is an issue with LPC1111FHN33/102,5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1111FHN33/102,5 part is unused and in its original packaging.
Return procedure for LPC1111FHN33/102,5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC1111FHN33/102,5 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

