NXP Semiconductors LPC1111FHN33/102K
- Part No.:
- LPC1111FHN33/102K
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 32-VQFN Exposed Pad
- Datasheet:
-
LPC1111FHN33/102K.pdf
- Description:
- IC MCU 32BIT 8KB FLASH 32HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:994
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC1111FHN33/102K from NXP Semiconductors is an ARM Cortex-M0 32-bit microcontroller in HVQFN33 package, delivering up to 50 MHz CPU operation, 8 kB flash, 2 kB SRAM, and integrated power profiles for low-power embedded control. It supports UART with RS-485, Fast-mode Plus I²C (1 Mbit/s), one SPI, 10-bit ADC (8-channel), and 28 GPIO pins - deployed in lighting control and alarm systems.
For engineers reviewing the LPC1111FHN33/102K datasheet, LPC1111FHN33/102K pinout, LPC1111FHN33/102K application, or LPC1111FHN33/102K equivalent, key selection factors include its HVQFN33 thermal-enhanced package, LPC1100L-series power management features, 28 GPIO with configurable open-drain mode, and compatibility with SWD debug interface.
Technical Context
The LPC1111FHN33/102K implements the ARM Cortex-M0 core with NVIC and system tick timer, operating at up to 50 MHz via internal 12 MHz RC oscillator (±1 %) or external crystal (1–25 MHz). Its clock generation includes a programmable PLL and watchdog oscillator (9.4 kHz–2.3 MHz).
It belongs to the LPC1100L series, enabling power profile optimization via boot ROM functions, windowed watchdog timer, and configurable open-drain GPIO - distinguishing it from base LPC1100 parts lacking these features. The device supports Sleep, Deep-sleep, and Deep power-down modes with wake-up on up to 13 functional pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0, 32-bit RISC architecture with hardware divide and Thumb-2 instruction set. |
| Max Clock Frequency | 50 MHz - enables real-time control loop execution within sub-10 µs latency for motor or sensor feedback. |
| Flash Memory | 8 kB - sufficient for compact firmware including bootloader, communication stack, and application logic. |
| SRAM | 2 kB - supports moderate data buffering, interrupt stacks, and small variable sets without external memory. |
| I/O Pins | 28 GPIO - all configurable as digital I/O, edge/level-sensitive interrupts, or peripheral functions (UART, I²C, SPI, ADC). |
| Analog Input | 10-bit ADC with 8 input channels - provides sufficient resolution for temperature, light, or voltage monitoring in white goods. |
| Serial Interfaces | 1 UART (RS-485 capable), 1 Fast-mode Plus I²C (1 Mbit/s), 1 SPI - meets industrial sensor node and lighting bus requirements. |
| Power Modes | Three reduced-power states (Sleep, Deep-sleep, Deep power-down) with wake-up on GPIO or timer - extends battery life in portable alarm systems. |
Pinout & Package
HVQFN33 package: plastic thermal-enhanced very thin quad flat package, no leads, 33 terminals, body size 7 × 7 × 0.85 mm. Exposed thermal pad improves heat dissipation in space-constrained lighting modules.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RESET/PIO0_0 | Reset input / GPIO | Active-low reset with internal pull-up; dual-function pin usable as general-purpose I/O after reset release. |
| XTALIN / XTALOUT | Clock oscillator inputs | Supports external crystal (1–25 MHz) or ceramic resonator; optional bypass for internal RC oscillator use. |
| SWDIO / PIO1_3 / AD4 | Debug / GPIO / ADC input | Multi-function pin: enables Serial Wire Debug during development and serves as ADC channel 4 in runtime. |
| PIO0_4 / SCL | I²C bus clock | Open-drain output with internal pull-up; supports Fast-mode Plus (1 Mbit/s) timing and multi-master arbitration. |
| PIO0_5 / SDA | I²C bus data | Open-drain bidirectional line; compatible with standard and Fast-mode Plus I²C peripherals in lighting control networks. |
| PIO1_6 / RXD | UART receive | Asynchronous serial input supporting RS-485 half-duplex mode with polarity control via software. |
| PIO1_7 / TXD | UART transmit | Drives RS-485 transceiver DE/RE lines via GPIO control for robust differential communication. |
| VDD / VSS | Power supply / ground | Single 1.8–3.6 V supply; dual VDD pins improve noise immunity; exposed thermal pad must be soldered to PCB ground plane. |
Key Features
| Feature | Design Value |
|---|---|
| Power Profiles in Boot ROM | One function call selects optimized performance/power trade-off - eliminates manual register configuration for sleep entry and wake-up latency tuning. |
| Windowed Watchdog Timer | Prevents runaway code by requiring service within defined time window - critical for fail-safe alarm system operation. |
| Configurable Open-Drain GPIO | Enables direct connection to I²C buses or wired-AND logic without external pull-ups - reduces BOM count in lighting driver designs. |
| High-Current Sink on I²C Pins | 20 mA sink capability on SCL/SDA - drives longer traces or multiple slave devices in industrial lighting networks. |
| SWD Debug Interface | Two-pin (SWCLK/SWDIO) debug access with minimal PCB footprint - accelerates firmware validation in compact embedded modules. |
Applications
| Lighting Control | Alarm Systems |
|---|---|
Use Scenario: Digital dimming and color mixing in LED luminaires using PWM outputs and ambient light sensing. IC Role / Device Role / Timing Role: Main controller executing lighting algorithms, managing I²C-connected sensors and drivers, and synchronizing multi-channel PWM via match registers. Use Value: 28 GPIO support independent PWM channels and sensor interfaces; 10-bit ADC resolves lux-level changes with <1% error across 0–1000 lux range. | Use Scenario: Intrusion detection panel with keypad scanning, siren control, and wireless module interfacing. IC Role / Device Role / Timing Role: Central security processor handling button debouncing, tamper switch monitoring, and UART-based RF module command framing. Use Value: Windowed WDT ensures immediate reset on firmware hang; 2 kB SRAM buffers encrypted event logs during power brownout. |
| eMetering | White Goods |
Use Scenario: Sub-metering of HVAC or outlet-level energy consumption in commercial buildings. IC Role / Device Role / Timing Role: Data acquisition unit sampling current/voltage via ADC, computing RMS values, and transmitting over RS-485 to gateway. Use Value: UART with fractional baud rate generator achieves precise 9600 bps over wide temperature range; 8 kB flash stores calibration coefficients and protocol stack. | Use Scenario: Motor speed control and user interface in washing machines or dishwashers. IC Role / Device Role / Timing Role: Real-time motor commutation controller using timer match outputs and ADC feedback from current sense resistors. Use Value: Four counter/timers with 13 match outputs enable simultaneous PWM generation for BLDC drive and UI LED blinking without CPU overhead. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1111FHN33/202 | Same package and pinout; 4 kB SRAM (vs. 2 kB); no power profiles or windowed WDT. | Suitable for applications needing larger RAM buffer but not requiring advanced power management. | Select when firmware requires >2 kB heap/stack and operates in fixed-performance mode without deep-sleep transitions. |
| LPC1111FHN33/103 | Same package and pinout; adds second SPI interface and windowed WDT; belongs to LPC1100XL series. | Better suited for systems requiring dual SPI (e.g., display + SD card) alongside enhanced safety monitoring. | Choose when design needs redundant communication paths and certified watchdog behavior per IEC 61508 SIL-2 requirements. |
Compared with LPC1111FHN33/102K, the /202 variant trades power management for extra RAM, while the /103 adds SPI and strengthens safety features - making the /102K optimal for cost-sensitive, low-power lighting and alarm nodes where single-SPI and boot-ROM power profiles deliver best balance.
Availability
LPC1111FHN33/102K is available at Aetrix Electronics and suitable for lighting control, alarm systems, eMetering, and white goods requiring stable component supply across extended temperature ranges (−40 °C to +85 °C).
Supply support for LPC1111FHN33/102K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC111x series was designed for cost-sensitive 8/16-bit MCU replacement in resource-constrained embedded systems, emphasizing low power, small footprint, and rapid time-to-market through ARM Cortex-M0 simplicity and NXP's mature toolchain support.
FAQ
What is the maximum operating frequency of the LPC1111FHN33/102K?
The LPC1111FHN33/102K operates at up to 50 MHz CPU frequency. This is achieved using either the internal 12 MHz RC oscillator (trimmed to ±1 % accuracy) or an external crystal (1–25 MHz) with an integrated PLL. The 50 MHz limit applies across the full industrial temperature range (−40 °C to +85 °C) and 1.8–3.6 V supply, ensuring deterministic real-time performance in lighting and alarm applications.
Does the LPC1111FHN33/102K support SWD debugging?
Yes, the LPC1111FHN33/102K supports Serial Wire Debug (SWD) via dedicated SWCLK and SWDIO pins (PIO0_10 and PIO1_3). These pins are multiplexed with GPIO and ADC functions but default to debug mode on power-up. SWD enables full breakpoint, step-through, and memory inspection capabilities using standard tools like LPC-Link2 or J-Link, with no additional hardware required beyond a two-wire connection.
How many ADC channels does the LPC1111FHN33/102K provide?
The LPC1111FHN33/102K integrates a 10-bit successive-approximation ADC with 8 input channels (AD0–AD7), accessible on dedicated pins in the HVQFN33 package. All 8 channels are simultaneously available and selectable via software-controlled multiplexer. The ADC supports burst mode, hardware trigger from timers, and conversion completion interrupts - enabling synchronized sampling in motor control or environmental monitoring applications using the LPC1111FHN33/102K.
What power management features are included in the LPC1111FHN33/102K?
The LPC1111FHN33/102K includes Sleep, Deep-sleep, and Deep power-down modes managed by an integrated PMU. As an LPC1100L-series part, it implements boot ROM power profiles - allowing one API call to configure optimal clock gating, peripheral disable, and wake-up sources. It also features a programmable windowed watchdog timer, brownout detection with four thresholds, and wake-up from Deep-sleep on up to 13 GPIO pins - all critical for battery-operated alarm systems built around the LPC1111FHN33/102K.
Is the LPC1111FHN33/102K pin-compatible with other HVQFN33 variants in the LPC111x family?
Yes, the LPC1111FHN33/102K shares identical pinout and package dimensions (7 × 7 × 0.85 mm HVQFN33) with all other FHN33-suffixed LPC111x parts, including LPC1111FHN33/101, /103, /201, /202, /203, and LPC1112FHN33 variants. Pin functions are consistent across these parts; differences lie only in flash/SRAM size, power profile availability, and peripheral enablement - enabling hardware reuse across product variants without PCB redesign.
LPC1111FHN33/102K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VQFN Exposed Pad
- Series:
- LPC1100L
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 28
- Program Memory Size:
- 8KB (8K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 8x10b SAR
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1111FHN33/102K FAQ
1.How can I place an order for LPC1111FHN33/102K through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1111FHN33/102K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1111FHN33/102K reliable?
The price and inventory of LPC1111FHN33/102K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1111FHN33/102K is usually 5 days.
3.What payment methods are accepted for LPC1111FHN33/102K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1111FHN33/102K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC1111FHN33/102K?
LPC1111FHN33/102K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1111FHN33/102K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1111FHN33/102K?
For technical support, including LPC1111FHN33/102K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1111FHN33/102K requirements.
6.How does Aetrix verify that LPC1111FHN33/102K is sourced from the original manufacturer or authorized distributors?
All LPC1111FHN33/102K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1111FHN33/102K meets industry standards.
7.What is the process for return or replacement of LPC1111FHN33/102K?
All LPC1111FHN33/102K units undergo pre-shipment inspection (PSI). If there is an issue with LPC1111FHN33/102K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1111FHN33/102K part is unused and in its original packaging.
Return procedure for LPC1111FHN33/102K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC1111FHN33/102K Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

