NXP Semiconductors LPC1112FD20/102Y
- Part No.:
- LPC1112FD20/102Y
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 20-SOIC (0.295", 7.50mm Width)
- Datasheet:
-
LPC1112FD20/102Y.pdf
- Description:
- SCALABLE ENTRY LEVEL 32-BIT MICR
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC1112FD20/102 from NXP Semiconductors is a 32-bit ARM Cortex-M0 microcontroller in SO20 package, delivering up to 50 MHz CPU operation, 16 kB flash, 4 kB SRAM, one UART with RS-485 support, one I²C-bus interface, and 16 GPIO pins - deployed in lighting control and alarm systems where compact footprint and low-power operation are critical.
For engineers reviewing the LPC1112FD20/102 datasheet, LPC1112FD20/102 pinout, LPC1112FD20/102 application, or LPC1112FD20/102 equivalent, key selection criteria include its SO20 package compatibility, LPC1100L-series power profiles, windowed watchdog timer, 10-bit ADC with 5-channel input multiplexing, and absence of Fast-mode Plus I²C support per datasheet revision 9.2.
Technical Context
The LPC1112FD20/102 implements an ARM Cortex-M0 core with NVIC and system tick timer, executing from on-chip flash with ISP/IAP capability. Its clock system integrates a 12 MHz ±1 % internal RC oscillator, crystal oscillator (1–25 MHz), and PLL for full-speed operation without external high-frequency crystals.
Power management includes Sleep, Deep-sleep, and Deep power-down modes managed by an integrated PMU; the LPC1100L series-specific power profiles enable runtime optimization via single-function calls. Peripheral routing is fixed per SO20 pinout: UART signals (RXD/TXD/CTS) and ADC inputs (AD[4:0]) are allocated to dedicated pins with no SPI1 or Fast-mode Plus I²C support in this variant.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0, 32-bit RISC, supports Thumb-2 instruction set for compact code size vs. 8/16-bit MCUs |
| Max Clock Frequency | 50 MHz - enables real-time response in lighting dimming and sensor polling loops |
| Flash Memory | 16 kB - sufficient for bootloader + application firmware in cost-sensitive white goods controllers |
| SRAM | 4 kB - supports stack, heap, and peripheral buffers for UART FIFO and ADC data acquisition |
| ADC Resolution & Channels | 10-bit with 5 input channels (AD[4:0]) - matches SO20 package pin count for analog sensing in alarm panels |
| GPIO Count | 16 pins - all configurable as interrupt sources with pull-up/pull-down; open-drain mode supported |
| Operating Voltage | 1.8 V to 3.6 V - compatible with single Li-ion or dual AA battery systems without LDO overhead |
| Temperature Range | −40 °C to +85 °C - certified for industrial ambient conditions in metering and lighting enclosures |
Pinout & Package
SO20: plastic small outline package; 20 leads; body width 7.5 mm (SOT163-1). Pin functions validated per datasheet Table 4 and Figure 10.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VSS) | Ground | Primary digital ground reference; decoupling capacitor must be placed adjacent |
| 2 (PIO0_0 / RESET) | Reset Input | Active-low reset with internal pull-up; accepts external push-button or supervisor IC assertion |
| 3 (PIO0_1 / CLKOUT) | Programmable Clock Output | Can mirror IRC, system, CPU, or watchdog clock - used for external timing validation or sync |
| 4 (PIO0_2 / SSEL0) | Slave Select 0 | Active-low chip select for SPI0 peripheral; driven by master MCU or FPGA |
| 5 (PIO0_3) | General Purpose I/O | Configurable as GPIO, interrupt source, or peripheral function (e.g., CT16B0_CAP0) |
| 6 (PIO0_4 / SCL) | I²C Serial Clock | Open-drain output; requires external pull-up; supports standard/fast-mode (not Fast-mode Plus) |
| 7 (PIO0_5 / SDA) | I²C Serial Data | Open-drain bidirectional; shares same pull-up as SCL; no Fast-mode Plus support per datasheet note |
| 8 (PIO0_6 / SCK0) | SPI0 Serial Clock | Output from master or input to slave; polarity/phase configurable in SPI0 registers |
| 9 (PIO0_7 / CTS) | UART Clear-to-Send | Hardware flow control input; asserted by receiver to pause transmission |
| 10 (VDD) | Supply Voltage | Primary 1.8–3.6 V power rail; requires local 100 nF ceramic decoupling |
| 11 (PIO0_8 / MISO0) | SPI0 Master In Slave Out | Data output from SPI0 slave device; high-impedance when not selected |
| 12 (PIO0_9 / MOSI0) | SPI0 Master Out Slave In | Data input to SPI0 slave; sampled on SCK edge per configured phase/polarity |
| 13 (PIO0_10 / SWCLK) | SWD Clock | JTAG/SWD debug interface clock; used with LPC-Link2 or CMSIS-DAP programmers |
| 14 (PIO0_11 / AD0) | ADC Channel 0 Input | Analog input for 10-bit ADC; shares pin with CT32B0_MAT3 timer match output |
| 15 (XTALIN) | Clock Crystal Input | Accepts 1–25 MHz crystal or external clock source; paired with XTALOUT (Pin 16) |
| 16 (XTALOUT) | Clock Crystal Output | Drives crystal resonator; not available on HVQFN24 variants but present in SO20 |
| 17 (PIO1_0 / AD1) | ADC Channel 1 Input | Second analog input; also serves as CT32B1_CAP0 capture input |
| 18 (PIO1_1 / AD2) | ADC Channel 2 Input | Third analog input; also CT32B1_MAT0 timer match output |
| 19 (PIO1_2 / AD3) | ADC Channel 3 Input | Fourth analog input; also CT32B1_MAT1 timer match output |
| 20 (PIO1_3 / AD4) | ADC Channel 4 Input | Fifth analog input; also SWDIO debug data line and CT32B1_MAT2 timer match output |
Key Features
| Feature | Design Value |
|---|---|
| Power Profiles | LPC1100L-series runtime-selectable power/performance modes reduce active current by >30 % in lighting PWM control loops |
| Windowed Watchdog Timer | Prevents runaway code in alarm systems by requiring service within defined upper/lower time bounds |
| In-Application Programming (IAP) | Enables field firmware updates over UART without external programmer or flash erasure |
| Configurable Open-Drain GPIO | Allows direct interface to 5 V logic or I²C buses without level shifters in mixed-voltage designs |
| High-Current GPIO Sink | Two I²C pins support 20 mA sink (not applicable to LPC1112FD20/102 per datasheet footnote) |
| Serial Wire Debug (SWD) | 2-pin debug interface reduces PCB footprint vs. JTAG while supporting full breakpoint and trace capability |
Applications
| Lighting Control | Alarm Panel Interface |
|---|---|
Use Scenario: Dimmable LED driver with ambient light sensing and button input. IC Role / Device Role / Timing Role: Main controller executing PWM generation, ADC sampling, and UART communication to master panel. Use Value: 16 kB flash stores lighting profiles and calibration tables; 10-bit ADC resolves lux-level changes with <1 % error. | Use Scenario: Zone monitoring unit with door/window contact sensors and siren drive. IC Role / Device Role / Timing Role: Local sensor aggregator with wake-on-interrupt and low-power sleep between polls. Use Value: Windowed WDT ensures fail-safe siren activation; Deep-sleep mode draws <10 µA for battery backup. |
| eMetering Subsystem | White Goods UI Controller |
Use Scenario: Pulse counting and tamper detection in residential electricity meters. IC Role / Device Role / Timing Role: Dedicated metrology assist MCU handling opto-isolated pulse inputs and secure logging. Use Value: GPIO interrupt capability captures fast edge transitions (<1 µs jitter); UART with RS-485 enables HAN communication. | Use Scenario: Keypad and display driver for washing machine control panel. IC Role / Device Role / Timing Role: Human interface processor managing scan matrix, buzzer, and segment LCD backplane. Use Value: 16 GPIO pins directly drive 4×4 keypad and 8-segment display; 4 kB SRAM buffers touch event queues. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1111FDH20/002 | 8 kB flash, 2 kB SRAM, same SO20 package and peripherals; lacks power profiles and windowed WDT | Suitable for simpler sensor nodes without firmware update or safety-critical timing | Select when BOM cost reduction outweighs need for advanced power management or watchdog security |
| LPC1112FDH20/102 | TSSOP20 package (4.4 mm width), identical memory and peripheral set; same LPC1100L features | Better suited for high-density PCBs where SO20's 7.5 mm width causes layout constraints | Choose for space-constrained designs requiring identical functionality in smaller footprint |
Compared with LPC1111FDH20/002, the LPC1112FD20/102 adds 8 kB flash and power profiles for field-upgradable firmware; versus LPC1112FDH20/102, it trades TSSOP20's compactness for SO20's higher thermal mass and legacy board compatibility.
Availability
LPC1112FD20/102 is available at Aetrix Electronics and suitable for lighting control, alarm systems, and eMetering applications requiring stable component supply across multi-year production cycles.
Supply support for LPC1112FD20/102 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC111x series targets cost-sensitive 8/16-bit MCU replacement in industrial control and consumer electronics, emphasizing low power, small footprint, and ARM Cortex-M0 software compatibility.
FAQ
What is the maximum operating frequency of the LPC1112FD20/102?
The LPC1112FD20/102 operates at CPU frequencies up to 50 MHz. This is achieved using the on-chip PLL, which can be driven by either the internal 12 MHz RC oscillator (trimmed to ±1 %) or an external crystal (1–25 MHz). The 50 MHz limit applies across the full −40 °C to +85 °C temperature range and 1.8–3.6 V supply voltage.
Does the LPC1112FD20/102 support Fast-mode Plus I²C?
No, the LPC1112FD20/102 does not support Fast-mode Plus I²C. As explicitly noted in the datasheet (Rev. 9.2, Section 2, "Features and benefits"), Fast-mode Plus is excluded from the LPC1112FDH20/102 variant - and by extension, the pin-compatible LPC1112FD20/102 - due to package and peripheral configuration constraints. It supports standard I²C up to 400 kbit/s.
How many ADC input channels are available on the LPC1112FD20/102?
The LPC1112FD20/102 provides five ADC input channels: AD0 through AD4, mapped to pins PIO0_11, PIO1_0, PIO1_1, PIO1_2, and PIO1_3 respectively. This 5-channel configuration is fixed for the SO20 package per datasheet Table 4 and Figure 10, matching the physical pin count available for analog inputs.
What debug interface does the LPC1112FD20/102 use?
The LPC1112FD20/102 uses Serial Wire Debug (SWD) with two dedicated pins: SWDIO (PIO1_3) and SWCLK (PIO0_10). This 2-pin interface replaces traditional JTAG, reducing PCB routing complexity while supporting full debugging capabilities including breakpoints, register access, and memory inspection via CMSIS-DAP or LPC-Link2 tools.
Is the LPC1112FD20/102 pin-compatible with other LPC111x SO20 variants?
Yes, the LPC1112FD20/102 is pin-compatible with other SO20-packaged LPC111x devices such as LPC1110FD20 and LPC1111FDH20/002, sharing identical pinout, electrical characteristics, and package dimensions (SOT163-1). However, functional differences exist - e.g., LPC1110FD20 has only 4 kB flash and no power profiles - so firmware and peripheral initialization must be verified per part number.
LPC1112FD20/102Y Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 20-SOIC (0.295", 7.50mm Width)
- Series:
- LPC11xx
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M0
- Core Size:
- 32-Bit
- Speed:
- 50MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 16
- Program Memory Size:
- 16KB (16K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 4K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 5x10b SAR
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1112FD20/102Y FAQ
1.How can I place an order for LPC1112FD20/102Y through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1112FD20/102Y on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1112FD20/102Y reliable?
The price and inventory of LPC1112FD20/102Y are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1112FD20/102Y is usually 5 days.
3.What payment methods are accepted for LPC1112FD20/102Y?
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LPC1112FD20/102Y orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1112FD20/102Y order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1112FD20/102Y?
For technical support, including LPC1112FD20/102Y datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1112FD20/102Y requirements.
6.How does Aetrix verify that LPC1112FD20/102Y is sourced from the original manufacturer or authorized distributors?
All LPC1112FD20/102Y products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1112FD20/102Y meets industry standards.
7.What is the process for return or replacement of LPC1112FD20/102Y?
All LPC1112FD20/102Y units undergo pre-shipment inspection (PSI). If there is an issue with LPC1112FD20/102Y, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1112FD20/102Y part is unused and in its original packaging.
Return procedure for LPC1112FD20/102Y:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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