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NXP Semiconductors LPC1112FDH28/102:5
- Part No.:
- LPC1112FDH28/102:5
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 28-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
LPC1112FDH28/102:5.pdf
- Description:
- LPC1112 - Scalable 32-bit Microc
- Quantity:
- Payment:
- Shipping:
Inventory:8,647
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Product details
Overview
LPC1112FDH28/102 from NXP Semiconductors is a 32-bit ARM Cortex-M0 microcontroller in TSSOP28 package, delivering up to 50 MHz CPU operation, 16 kB flash, 4 kB SRAM, one UART with RS-485 support, one I²C-bus interface, and 22 GPIO pins - deployed in lighting control and alarm systems requiring compact, low-power embedded processing.
For engineers reviewing the LPC1112FDH28/102 datasheet, LPC1112FDH28/102 pinout, LPC1112FDH28/102 application, or LPC1112FDH28/102 equivalent, this page provides verified technical context, package-specific pin functions, power profile support, ADC channel count, and validated alternative options for cost-sensitive industrial MCU selection.
Technical Context
The LPC1112FDH28/102 implements an ARM Cortex-M0 core with Nested Vectored Interrupt Controller (NVIC) and Serial Wire Debug, operating at up to 50 MHz using internal RC oscillator (1 % trimmed) or external crystal (1–25 MHz). It integrates a programmable windowed watchdog timer and Power Management Unit supporting Sleep, Deep-sleep, and Deep power-down modes.
Peripheral integration includes a 10-bit ADC with 6 input channels, four general-purpose timers (two 32-bit, two 16-bit), high-current GPIO drivers (20 mA sink on I²C pins), and configurable open-drain mode - all enabled via boot ROM power profiles specific to the LPC1100L series.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0, enabling Thumb-2 instruction set compatibility and deterministic interrupt latency for real-time control. |
| Max Clock Frequency | 50 MHz, achievable via PLL from internal 12 MHz RC oscillator or external crystal - no high-frequency crystal required. |
| Flash Memory | 16 kB on-chip flash with ISP/IAP support, sufficient for firmware updates without external programming hardware. |
| SRAM | 4 kB SRAM, allocated for stack, heap, and peripheral buffers in resource-constrained embedded applications. |
| GPIO Pins | 22 general-purpose I/O pins with configurable pull-up/pull-down and edge/level-sensitive interrupt capability. |
| ADC | 10-bit successive approximation ADC with 6 multiplexed input channels, suitable for sensor signal acquisition in white goods. |
| I²C Interface | Full I²C-bus specification + Fast-mode Plus (1 Mbit/s), enabling high-speed communication with EEPROMs and sensors. |
| UART | RS-485/EIA-485 UART with fractional baud rate generation and internal FIFO, supporting robust multi-drop industrial bus networks. |
Pinout & Package
TSSOP28 package: plastic thin shrink small outline package, 28 leads, body width 4.4 mm, 1.0 mm maximum height, lead pitch 0.65 mm - optimized for automated PCB assembly and thermal performance in space-constrained designs.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (VDD) | Power supply | Primary 1.8–3.6 V supply rail; decoupling capacitor placement critical for stable core and analog operation. |
| 2 (PIO0_0/RESET) | Reset input | Active-low reset pin; also functions as GPIO0_0 after reset release - enables dual-role board-level reset signaling. |
| 3 (PIO0_1/CLKOUT) | Programmable clock output | Outputs system, IRC, CPU, or watchdog clock divided by configurable prescaler - used for timing validation or peripheral sync. |
| 4 (PIO0_2/SSEL0) | Slave select for SPI0 | Enables slave mode on SPI0; supports hardware-controlled chip select for daisy-chained peripherals. |
| 5 (PIO0_3) | General-purpose I/O | Configurable as digital input/output with interrupt capability - used for status LEDs or push-button inputs. |
| 6 (PIO0_4/SCL) | I²C clock line | Open-drain output with internal pull-up option; supports Fast-mode Plus 1 Mbit/s data rates in master/slave roles. |
| 7 (PIO0_5/SDA) | I²C data line | Open-drain bidirectional data line; shares same electrical characteristics and timing as SCL for synchronized bus operation. |
| 8 (PIO0_6/SCK0) | SPI0 clock | Master or slave clock source for SPI0; polarity and phase configurable per frame for legacy peripheral compatibility. |
| 9 (PIO0_7/CTS) | UART clear-to-send | Hardware flow control input for UART; asserts when receiver buffer has space - prevents overrun in high-throughput serial links. |
| 10 (PIO0_8/MISO0) | SPI0 master-in-slave-out | Data output from SPI0 slave device; tri-stated when not selected - avoids bus contention in multi-peripheral configurations. |
| 11 (PIO0_9/MOSI0) | SPI0 master-out-slave-in | Data input to SPI0 slave; sampled on SCK edge - supports full-duplex communication with sensors and displays. |
| 12 (PIO0_10/SWCLK) | SWD clock | JTAG/SWD debug clock input; enables non-intrusive firmware debugging and flash programming during development. |
| 13 (PIO0_11/AD0) | ADC input channel 0 | Analog input for 10-bit ADC; supports single-ended measurement with internal reference - used for temperature or voltage monitoring. |
| 14 (VSS) | Ground | Digital ground reference; must be connected to PCB ground plane with low-inductance path to minimize noise coupling. |
| 15 (XTALIN) | Clock crystal input | Connects to external crystal or oscillator; requires load capacitors per crystal spec - enables precise timing for UART and ADC sampling. |
| 16 (XTALOUT) | Clock crystal output | Drives crystal resonator; not available on LPC1112FDH20/102 but present on TSSOP28 variant - confirms oscillator functionality. |
| 17 (R/PIO1_0) | ADC input / GPIO | Shared analog/digital pin; configured as AD1 input or PIO1_0 - allows flexible pin reuse in mixed-signal designs. |
| 18 (R/PIO1_1) | ADC input / GPIO | Shared analog/digital pin; configured as AD2 input or PIO1_1 - expands analog sensing capability without extra pins. |
| 19 (R/PIO1_2) | ADC input / GPIO | Shared analog/digital pin; configured as AD3 input or PIO1_2 - supports multi-channel sensor arrays in compact layouts. |
| 20 (SWDIO/PIO1_3) | SWD data I/O | Bidirectional debug data line; also functions as AD4 and CT32B1_MAT2 - enables debug access without dedicated debug header footprint. |
| 21 (PIO1_4/AD5/WAKEUP) | ADC input / wake-up source | Configurable as AD5 input or wake-up trigger from Deep-sleep - enables low-power sensor polling with fast wake latency. |
| 22 (PIO1_5/RTS) | UART request-to-send | Hardware flow control output; signals transmitter readiness - essential for reliable RS-485 half-duplex bus arbitration. |
| 23 (PIO1_6/RXD) | UART receive data | Asynchronous serial input; supports RS-485 differential receiver interface - used for command reception in industrial controllers. |
| 24 (PIO1_7/TXD) | UART transmit data | Asynchronous serial output; drives RS-485 transceiver DE/RE pins via GPIO - enables full-duplex or half-duplex bus control. |
| 25 (PIO1_8) | Timer capture/compare | CT16B1_CAP0 input or CT16B1_MAT0 output - supports PWM generation or pulse-width measurement for motor control. |
| 26 (PIO1_9) | Timer match output | CT16B1_MAT0 output; generates precise timing events - used for LED dimming or periodic sensor sampling triggers. |
| 27 (PIO1_10/AD6) | ADC input channel 6 | 10-bit analog input; extends ADC channel count to six - accommodates multi-sensor inputs in alarm system front-ends. |
| 28 (VDD) | Power supply | Secondary 1.8–3.6 V supply rail; decoupled separately to reduce switching noise coupling into analog sections. |
Key Features
| Feature | Design Value |
|---|---|
| Power profiles in boot ROM | One function call configures CPU/peripheral clocks, voltage scaling, and sleep modes - reduces firmware development time for low-power optimization. |
| Windowed watchdog timer | Prevents runaway code execution while allowing valid long-duration operations - critical for fail-safe alarm and lighting control firmware. |
| Configurable open-drain mode | Enables I²C-bus and 1-wire interface implementation without external pull-ups - saves BOM cost and PCB area in sensor nodes. |
| High-current GPIO sinks | 20 mA sink capability on I²C pins supports direct LED driving or relay coil control - eliminates need for external driver transistors. |
| In-Application Programming (IAP) | Allows firmware updates over UART or I²C without halting application - enables field upgrades in deployed lighting and metering devices. |
| Serial Wire Debug (SWD) | Two-pin debug interface replaces JTAG, freeing GPIO pins for application use - maximizes I/O availability in TSSOP28 footprint. |
Applications
| Lighting Control | Alarm System Front-End |
|---|---|
Use Scenario: Dimmable LED driver with ambient light sensing and wireless command reception. IC Role / Device Role / Timing Role: Main controller executing PWM dimming logic, reading ADC-based light sensor, and parsing UART commands from RF module. Use Value: 22 GPIO enable direct LED string control and sensor interfacing; 6-channel ADC supports multi-zone ambient sensing; UART RS-485 mode ensures noise-immune command link. | Use Scenario: Door/window contact monitoring with tamper detection and local siren activation. IC Role / Device Role / Timing Role: Sensor aggregator managing reed switch inputs, detecting enclosure opening via GPIO interrupts, and driving piezo siren via PWM. Use Value: Edge-sensitive GPIO interrupts provide sub-10 µs response to intrusion; windowed WDT guarantees recovery from fault conditions; 16 kB flash stores encrypted event logs. |
| eMetering Subsystem | White Goods UI Panel |
Use Scenario: Pulse counting and tariff calculation unit in smart electricity meter with optical isolation interface. IC Role / Device Role / Timing Role: Dedicated metering co-processor capturing kWh pulses via GPIO counter/timer, storing tariff tables in flash, and communicating via isolated UART. Use Value: Four 32/16-bit timers support simultaneous pulse capture and real-time clock; 1.8–3.6 V operation matches isolated power supply rails; I²C interfaces with RTC and display driver. | Use Scenario: Keypad scan and display update engine for refrigerator control panel with touch feedback. IC Role / Device Role / Timing Role: User interface processor scanning matrix keypad, driving segmented LCD via GPIO, and generating tactile feedback via PWM buzzer. Use Value: 22 GPIO support 4×4 keypad + 8-segment display + status LEDs; 10-bit ADC reads potentiometer for temperature setting; low-power Deep-sleep mode extends battery life in backup operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1111FDH20/002 | 8 kB flash, 2 kB SRAM, 16 GPIO, TSSOP20 package - smaller memory and I/O count. | Targeted at simpler sensor nodes with minimal firmware and fewer peripherals. | Select when design fits within 8 kB code size and requires only 16 GPIO - reduces PCB area and BOM cost. |
| LPC1114FDH28/102 | 32 kB flash, 4 kB SRAM, same TSSOP28 package and peripheral set - double flash capacity. | Suitable for applications needing larger bootloader, OTA update partition, or complex protocol stacks. | Choose when future firmware expansion or dual-bank OTA updates are required - maintains identical pinout and layout. |
Compared with LPC1111FDH20/002, the LPC1112FDH28/102 provides 100 % more flash and 6 additional GPIO for enhanced feature integration; compared with LPC1114FDH28/102, it offers identical I/O and peripherals at lower memory cost - optimizing BOM for mid-complexity industrial controls.
Availability
LPC1112FDH28/102 is available at Aetrix Electronics and suitable for lighting control, alarm systems, and eMetering applications requiring stable component supply, long-term lifecycle support, and consistent parametric performance across production batches.
Supply support for LPC1112FDH28/102 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC111x series targets cost-sensitive 8/16-bit replacement applications, emphasizing low power, simple toolchain adoption, and rapid time-to-market for industrial control and consumer electronics.
FAQ
What is the maximum operating frequency of the LPC1112FDH28/102?
The LPC1112FDH28/102 operates at up to 50 MHz using its integrated PLL, which can be clocked from either the internal 12 MHz RC oscillator (trimmed to ±1 %) or an external crystal (1–25 MHz range). This eliminates the need for high-frequency crystals while maintaining timing precision for UART and ADC operations in the LPC1112FDH28/102.
Does the LPC1112FDH28/102 support In-Application Programming (IAP)?
Yes, the LPC1112FDH28/102 supports In-Application Programming via its on-chip bootloader, enabling firmware updates without halting the running application. This capability is implemented in ROM and accessible through UART or I²C interfaces, making it ideal for remote updates in deployed lighting and alarm systems using the LPC1112FDH28/102.
How many ADC input channels does the LPC1112FDH28/102 provide?
The LPC1112FDH28/102 provides six ADC input channels (AD0–AD6), mapped to specific GPIO pins in the TSSOP28 package. This 10-bit successive approximation ADC supports single-ended measurements with internal reference, enabling simultaneous monitoring of multiple sensors in white goods and eMetering applications using the LPC1112FDH28/102.
Is the LPC1112FDH28/102 compatible with the LPC1114FDH28/102 in terms of pinout and software?
Yes, the LPC1112FDH28/102 and LPC1114FDH28/102 share identical TSSOP28 pinouts, peripheral register maps, and boot ROM features, including power profiles and windowed watchdog timer. Firmware developed for the LPC1112FDH28/102 runs unchanged on the LPC1114FDH28/102, enabling seamless migration to higher flash capacity without PCB redesign.
What power-saving modes are supported by the LPC1112FDH28/102?
The LPC1112FDH28/102 supports three reduced-power modes: Sleep, Deep-sleep, and Deep power-down. Wake-up from Deep-sleep is possible via up to 13 functional GPIO pins, and power profiles in boot ROM allow one function call to configure optimal clocking and voltage settings - critical for battery-backed alarm and metering applications using the LPC1112FDH28/102.
LPC1112FDH28/102:5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 28-TSSOP (0.173", 4.40mm Width)
- Series:
- LPC11xx
- Packaging:
- Bulk
- Product Status:
- Active
- Programmable:
- -
- Core Processor:
- ARM® Cortex®-M0
- Core Size:
- 32-Bit
- Speed:
- 50MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 22
- Program Memory Size:
- 16KB (16K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 4K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 6x10b SAR
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1112FDH28/102:5 FAQ
1.How can I place an order for LPC1112FDH28/102:5 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1112FDH28/102:5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1112FDH28/102:5 reliable?
The price and inventory of LPC1112FDH28/102:5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1112FDH28/102:5 is usually 5 days.
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5.How can I obtain technical support or documentation for LPC1112FDH28/102:5?
For technical support, including LPC1112FDH28/102:5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1112FDH28/102:5 requirements.
6.How does Aetrix verify that LPC1112FDH28/102:5 is sourced from the original manufacturer or authorized distributors?
All LPC1112FDH28/102:5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1112FDH28/102:5 meets industry standards.
7.What is the process for return or replacement of LPC1112FDH28/102:5?
All LPC1112FDH28/102:5 units undergo pre-shipment inspection (PSI). If there is an issue with LPC1112FDH28/102:5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1112FDH28/102:5 part is unused and in its original packaging.
Return procedure for LPC1112FDH28/102:5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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