NXP Semiconductors LPC1112FHN24/202J
- Part No.:
- LPC1112FHN24/202J
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 24-VFQFN Exposed Pad
- Datasheet:
-
LPC1112FHN24/202J.pdf
- Description:
- IC MCU 32BIT 16KB FLASH 24HVQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC1112FHN24/202 from NXP Semiconductors is a 32-bit ARM Cortex-M0 microcontroller in a 24-pin HVQFN package, featuring 16 kB flash, 4 kB SRAM, one UART with RS-485 support, one I²C-bus interface (Fast-mode Plus), one SPI, four timers, and a 10-bit ADC with six input channels - deployed in lighting control and alarm systems where compact size and low-power operation are critical.
For engineers reviewing the LPC1112FHN24/202 datasheet, LPC1112FHN24/202 pinout, LPC1112FHN24/202 application, or LPC1112FHN24/202 equivalent, this page delivers verified technical context, validated pin functions, real-world use cases, and confirmed alternative options for industrial embedded design and volume procurement.
Technical Context
The LPC1112FHN24/202 implements an ARM Cortex-M0 core operating at up to 50 MHz, with integrated NVIC and Serial Wire Debug. It uses a 12 MHz internal RC oscillator trimmed to ±1 % accuracy as primary clock source, and supports crystal oscillators from 1–25 MHz.
Its peripheral set includes a programmable windowed watchdog timer (WDT), power management unit (PMU) enabling Sleep/Deep-sleep/Deep power-down modes, and GPIO with configurable pull-up/pull-down and open-drain capability - all aligned with the LPC1100L series' focus on cost-sensitive, low-power 8/16-bit replacement applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0, 32-bit RISC, up to 50 MHz operation |
| Flash Memory | 16 kB on-chip flash with ISP/IAP support for field firmware updates |
| SRAM | 4 kB general-purpose static RAM for data and stack storage |
| ADC | 10-bit successive approximation ADC with 6 multiplexed input channels |
| I²C Interface | One Fast-mode Plus I²C-bus supporting 1 Mbit/s data rate and multi-address recognition |
| GPIO Pins | 19 general-purpose I/O pins with configurable pull-up/pull-down and open-drain mode |
| Package | HVQFN24: 4 mm × 4 mm × 0.85 mm, 24-terminal thermal-enhanced quad flat no-lead |
Pinout & Package
HVQFN24 package: 4 mm × 4 mm body, 0.5 mm pitch, 24 terminals, exposed thermal pad, RoHS-compliant plastic construction per SOT616-3.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Power supply | Single 1.8–3.6 V supply rail; two VDD pins provide decoupling flexibility |
| VSS | Ground | Two dedicated ground terminals for noise reduction and signal integrity |
| RESET/PIO0_0 | Reset input / GPIO | Active-low reset with internal pull-up; also serves as general-purpose I/O |
| XTALIN | Clock input | Connects to external crystal or oscillator; requires external load capacitors |
| SWDIO/PIO1_3/AD4/CT32B1_MAT2 | Debug I/O / ADC / Timer | Multi-function pin supporting SWD debug, analog input, and timer match output |
| PIO0_7/CTS | UART control | Clear-to-send input for hardware flow control in RS-485/EIA-485 UART |
| PIO1_6/RXD/CT32B0_MAT0 | UART receive / Timer | Primary UART data input and 32-bit timer match channel 0 output |
| PIO1_7/TXD/CT32B0_MAT1 | UART transmit / Timer | Primary UART data output and 32-bit timer match channel 1 output |
| PIO0_4/SCL | I²C clock | Open-drain I²C serial clock line; supports Fast-mode Plus 1 Mbit/s |
| PIO0_5/SDA | I²C data | Open-drain I²C serial data line; supports Fast-mode Plus 1 Mbit/s |
| PIO0_6/SCK0 | SPI clock | Serial clock output for SPI0 master mode; also usable as GPIO |
| PIO0_8/MISO0/CT16B0_MAT0 | SPI input / Timer | MISO for SPI0 and 16-bit timer match channel 0 output |
| PIO0_9/MOSI0/CT16B0_MAT1 | SPI output / Timer | MOSI for SPI0 and 16-bit timer match channel 1 output |
| PIO0_2/SSEL0/CT16B0_CAP0 | SPI select / Timer | Slave select for SPI0 and 16-bit timer capture input 0 |
| PIO1_4/AD5/CT32B1_MAT3/WAKEUP | ADC input / Timer / Wakeup | Analog input channel 5, timer match output, and Deep-sleep wake-up source |
| PIO1_11/AD7 | ADC input | Analog input channel 7; available only on HVQFN24 and larger packages |
| PIO2_0/DTR | UART control | Data terminal ready output for modem control signaling |
| PIO2_2/DCD/MISO1 | UART control / SPI input | Data carrier detect input or MISO for SPI1 (second SPI not available on HVQFN24) |
| PIO2_3/RI/MOSI1 | UART control / SPI output | Ring indicator input or MOSI for SPI1 (second SPI not available on HVQFN24) |
| PIO2_4 | GPIO | Dedicated general-purpose I/O with interrupt capability |
| PIO2_5 | GPIO | Dedicated general-purpose I/O with interrupt capability |
| PIO3_2 | GPIO | Dedicated general-purpose I/O with interrupt capability |
| PIO3_4 | GPIO | Dedicated general-purpose I/O with interrupt capability |
| PIO3_5 | GPIO | Dedicated general-purpose I/O with interrupt capability |
Key Features
| Feature | Design Value |
|---|---|
| Power profiles in boot ROM | One function call selects optimized performance/power trade-off for specific application workloads |
| Windowed watchdog timer | Prevents runaway code by requiring periodic service within defined time windows |
| Configurable open-drain GPIO | Enables direct connection to I²C bus without external pull-ups in standard configurations |
| High-current GPIO drivers | 20 mA sink capability on I²C pins supports robust bus driving under load |
| Serial Wire Debug (SWD) | Two-pin debug interface reduces PCB footprint versus JTAG while retaining full debug functionality |
Applications
| Lighting Control | Alarm Systems |
|---|---|
Use Scenario: Digital dimming and color mixing in LED driver modules using PWM outputs and ambient light sensing. IC Role / Device Role / Timing Role: Main controller executing lighting algorithms, managing I²C-connected sensors, and generating precise PWM timing via CT16B0/CT32B0 timers. Use Value: 19 GPIOs enable direct LED string control and sensor interfacing; 10-bit ADC resolves ambient light changes with <1% error over 0–100 lux range. | Use Scenario: Intrusion detection panel with keypad scanning, siren activation, and wired zone monitoring. IC Role / Device Role / Timing Role: Central MCU handling keypad matrix scan, UART-based communication to central hub, and WDT-monitored system supervision. Use Value: Windowed WDT ensures fail-safe behavior during zone polling; 16 kB flash accommodates encrypted zone logic and event logging firmware. |
| eMetering | White Goods |
Use Scenario: Sub-metering node in smart energy distribution, measuring voltage/current via external ADC and reporting via UART RS-485. IC Role / Device Role / Timing Role: Data acquisition coordinator interfacing with metrology ICs and transmitting data over half-duplex RS-485 bus. Use Value: UART with fractional baud rate generator achieves exact 9600 bps over wide temperature range; 4 kB SRAM buffers 32+ meter readings before transmission. | Use Scenario: Motor control and user interface in washing machine control board, managing water valves, drum rotation, and display. IC Role / Device Role / Timing Role: System supervisor coordinating motor driver signals, reading front-panel buttons, and driving 7-segment display via GPIO. Use Value: 19 GPIOs support direct button matrix and LED segment drive; Deep-sleep mode reduces standby current to <1 µA for energy compliance. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1111FHN24/102 | 8 kB flash, 2 kB SRAM, same HVQFN24 package and peripheral set | Lower memory capacity limits firmware complexity and feature depth | Select when application firmware fits within 8 kB and cost sensitivity outweighs memory headroom |
| LPC1112FHN33/202 | Same flash/SRAM, HVQFN33 package with 33 terminals and 28 GPIOs | Additional GPIOs and ADC channels enable expanded sensor or actuator interfaces | Select when design requires >19 GPIOs or needs AD[7:0] instead of AD[5:0] for higher-resolution analog sensing |
Compared with LPC1111FHN24/102, the LPC1112FHN24/202 provides double flash and SRAM for richer firmware; compared with LPC1112FHN33/202, it trades 9 GPIOs and 2 ADC inputs for smaller PCB area and lower assembly cost in space-constrained designs.
Availability
LPC1112FHN24/202 is available at Aetrix Electronics and suitable for lighting control, alarm systems, and eMetering requiring stable component supply across production lifecycles.
Supply support for LPC1112FHN24/202 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, delivering secure, scalable solutions for automotive, industrial, IoT, and mobile applications.
The LPC111x series targets cost-sensitive embedded applications replacing legacy 8/16-bit MCUs, emphasizing low power, small footprint, and ARM Cortex-M0 software compatibility for rapid migration.
FAQ
What is the maximum operating frequency of the LPC1112FHN24/202?
The LPC1112FHN24/202 operates at a maximum CPU frequency of 50 MHz. This is achieved using either the internal 12 MHz RC oscillator (trimmed to ±1 %) with PLL multiplication or an external crystal oscillator ranging from 1 MHz to 25 MHz. The PLL allows full-speed operation without requiring a high-frequency crystal, simplifying clock design and reducing BOM cost.
Does the LPC1112FHN24/202 support in-system programming (ISP)?
Yes, the LPC1112FHN24/202 supports In-System Programming (ISP) via its built-in bootloader, enabling firmware updates through UART without requiring a dedicated programmer. This capability is implemented in ROM and works with standard serial interfaces, allowing field upgrades and simplified manufacturing programming workflows for the LPC1112FHN24/202.
How many ADC input channels are available on the LPC1112FHN24/202?
The LPC1112FHN24/202 provides six ADC input channels (AD[5:0]), as confirmed in Table 2 and Figure 1 block diagram notes. This configuration is specific to the HVQFN24 package variant; larger packages like LQFP48 support up to eight channels. All six channels are accessible on dedicated pins and share a single 10-bit successive approximation converter.
Is the LPC1112FHN24/202 pin-compatible with other LPC111x HVQFN variants?
No, the LPC1112FHN24/202 is not pin-compatible with other HVQFN variants such as LPC1112FHN33/202. The HVQFN24 package has 24 terminals with a distinct pinout (Table 6, Figure 11), while HVQFN33 packages have 33 terminals and different signal assignments - including additional GPIOs, ADC channels, and timer functions not routed to the 24-pin layout.
What power-saving modes does the LPC1112FHN24/202 support?
The LPC1112FHN24/202 supports three reduced-power modes: Sleep, Deep-sleep, and Deep power-down. In Deep-sleep mode, it can wake via up to 13 functional pins; Deep power-down reduces current to sub-μA levels. Power profiles in boot ROM allow runtime selection of optimized performance/power settings - a feature enabled by the LPC1100L series designation in the LPC1112FHN24/202 part number suffix.
LPC1112FHN24/202J Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 24-VFQFN Exposed Pad
- Series:
- LPC1100L
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 19
- Program Memory Size:
- 16KB (16K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 6x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1112FHN24/202J FAQ
1.How can I place an order for LPC1112FHN24/202J through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1112FHN24/202J on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1112FHN24/202J reliable?
The price and inventory of LPC1112FHN24/202J are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1112FHN24/202J is usually 5 days.
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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1112FHN24/202J?
For technical support, including LPC1112FHN24/202J datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1112FHN24/202J requirements.
6.How does Aetrix verify that LPC1112FHN24/202J is sourced from the original manufacturer or authorized distributors?
All LPC1112FHN24/202J products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1112FHN24/202J meets industry standards.
7.What is the process for return or replacement of LPC1112FHN24/202J?
All LPC1112FHN24/202J units undergo pre-shipment inspection (PSI). If there is an issue with LPC1112FHN24/202J, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1112FHN24/202J part is unused and in its original packaging.
Return procedure for LPC1112FHN24/202J:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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