NXP Semiconductors LPC1112FHN33/202K
- Part No.:
- LPC1112FHN33/202K
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 32-VQFN Exposed Pad
- Datasheet:
-
LPC1112FHN33/202K.pdf
- Description:
- IC MCU 32BIT 16KB FLASH 32HVQFN
- Quantity:
- Payment:

- Shipping:

Inventory:1,250
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Product details
Overview
LPC1112FHN33/202K from NXP Semiconductors is a 32-bit ARM Cortex-M0 microcontroller in HVQFN33 package, delivering up to 50 MHz CPU operation, 16 kB flash, 4 kB SRAM, one UART with RS-485 support, one I²C-bus interface (Fast-mode Plus), and 28 GPIO pins - deployed in lighting control and alarm systems requiring compact, low-power embedded processing.
For engineers reviewing the LPC1112FHN33/202K datasheet, LPC1112FHN33/202K pinout, LPC1112FHN33/202K application, or LPC1112FHN33/202K equivalent, key selection factors include its LPC1100L-series power profiles, windowed watchdog timer, configurable open-drain GPIO mode, and compatibility with SWD debug interface for rapid firmware development.
Technical Context
The LPC1112FHN33/202K implements an ARM Cortex-M0 core with NVIC and system tick timer, executing instructions at up to 50 MHz using either internal 12 MHz RC oscillator (±1 %) or external crystal (1–25 MHz). Its clock generation includes PLL for full-speed operation and programmable watchdog oscillator (9.4 kHz–2.3 MHz).
It integrates a Power Management Unit supporting Sleep, Deep-sleep, and Deep power-down modes, with wake-up capability via up to 13 functional pins. The device belongs to the LPC1100L series, enabling power profile optimization via single-function ROM calls and featuring a windowed WDT not present in base LPC1100 variants.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0, enabling Thumb-2 instruction set compatibility and deterministic interrupt latency for real-time control. |
| Max Clock Frequency | 50 MHz - supports high-throughput peripheral handling without external clock multiplication. |
| Flash Memory | 16 kB - sufficient for bootloader + application firmware in cost-sensitive industrial sensor nodes. |
| SRAM | 4 kB - accommodates stack, heap, and real-time data buffers for multi-tasking RTOS environments. |
| I/O Pins | 28 GPIO - includes configurable pull-up/pull-down and open-drain mode for direct interfacing with I²C, RS-485 transceivers, and discrete logic. |
| Analog Input | 10-bit ADC with 8-channel multiplexing - enables direct sensing of temperature, light, or voltage levels without external signal conditioning. |
| Serial Interfaces | 1 UART (RS-485 capable), 1 I²C (Fast-mode Plus, 1 Mbit/s), 1 SPI - provides robust communication for distributed control networks. |
Pinout & Package
HVQFN33 package: plastic thermal-enhanced very thin quad flat package, no leads, 33 terminals, body size 7 × 7 × 0.85 mm, exposed thermal pad for improved heat dissipation in space-constrained PCB layouts.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD | Power supply | Single 1.8–3.6 V rail powers core and I/O; decoupling required per datasheet layout guidelines. |
| VSS | GND | Ground reference for analog/digital domains; connects to exposed thermal pad for thermal and EMI performance. |
| RESET/PIO0_0 | Reset input / GPIO | Active-low reset with internal pull-up; dual-function pin allows flexible board-level reset signaling or general-purpose use. |
| XTALIN / XTALOUT | Clock input/output | Supports external crystal (1–25 MHz) or ceramic resonator; optional bypass for internal RC oscillator usage. |
| SWDIO / PIO1_3 | Debug I/O | Two-pin Serial Wire Debug interface enables non-intrusive programming and real-time debugging without dedicated JTAG pins. |
| SWCLK / PIO0_10 | Debug clock | Provides synchronous clock for SWD transactions; shares pin with SCK0 and CT16B0_MAT2 for resource-efficient routing. |
| PIO0_4 / SCL | I²C clock | Open-drain output with internal pull-up option; supports Fast-mode Plus (1 Mbit/s) for high-speed sensor bus communication. |
| PIO0_5 / SDA | I²C data | Open-drain bidirectional line; compatible with standard and Fast-mode Plus I²C peripherals across mixed-voltage systems. |
| PIO1_6 / RXD | UART receive | Asynchronous serial input with fractional baud rate generator - enables precise timing for legacy RS-485 master/slave protocols. |
| PIO1_7 / TXD | UART transmit | Drives RS-485 transceiver DE/RE lines via GPIO control; supports half-duplex differential bus topology. |
Key Features
| Feature | Design Value |
|---|---|
| Power Profiles in Boot ROM | Enables runtime selection of optimized performance/power trade-offs (e.g., low-latency vs. ultra-low-power mode) via single API call - no custom firmware tuning required. |
| Windowed Watchdog Timer | Prevents runaway code by requiring service within defined upper/lower time bounds - critical for fail-safe alarm and metering applications. |
| Configurable Open-Drain GPIO | Allows direct connection to I²C buses, wired-AND logic, or RS-485 enable lines without external pull-ups or level shifters. |
| High-Current Sink on I²C Pins | 20 mA sink capability on SCL/SDA supports driving longer traces or multiple slave devices without external buffers. |
| Wake-Up from Deep-Sleep | Up to 13 GPIO pins can trigger wake-up events - reduces system power to µA range while retaining responsive event detection. |
Applications
| Lighting Control | Alarm System Interface |
|---|---|
Use Scenario: LED driver board in smart ceiling fixture with dimming, color tuning, and occupancy sensing. IC Role / Device Role / Timing Role: Main controller managing PWM outputs, I²C sensor reads, and DALI/DMX protocol translation. Use Value: 28 GPIO and integrated 10-bit ADC eliminate external mux/ADC, reducing BOM count and PCB area. | Use Scenario: Zone monitoring unit in commercial intrusion detection system with door/window contacts and PIR sensors. IC Role / Device Role / Timing Role: Local decision node polling inputs, debouncing signals, and transmitting alerts over RS-485 backbone. Use Value: Windowed WDT ensures reliable fault recovery during transient EMI events common in security installations. |
| eMetering Front-End | White Goods UI Panel |
Use Scenario: Pulse-counting and tamper-detection module in residential electricity meter with optical isolation. IC Role / Device Role / Timing Role: Isolated data acquisition engine capturing kWh pulses and detecting magnetic tampering via Hall sensor. Use Value: Deep-sleep mode with GPIO wake-up achieves <10 µA standby current - extends battery life in backup-powered meters. | Use Scenario: Keypad and display controller in washing machine control panel with LED indicators and buzzer feedback. IC Role / Device Role / Timing Role: Dedicated UI processor handling button scan, LED PWM, buzzer tone generation, and serial comms to main MCU. Use Value: Single 3.3 V supply and 16 kB flash support complete UI firmware with diagnostics and firmware update capability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1112FHN33/102 | Same package and pinout, but LPC1100 series (no power profiles or windowed WDT); 2 kB SRAM instead of 4 kB. | Suitable for simpler firmware with lower memory footprint; lacks runtime power optimization and enhanced watchdog safety. | Select when cost sensitivity outweighs need for advanced power management or safety-critical WDT behavior. |
| LPC1112FHN33/203 | LPC1100XL series variant: adds second SPI interface and 2× ADC channels (8 vs. 5), same 16 kB flash and 4 kB SRAM. | Better suited for designs requiring dual SPI peripherals (e.g., display + SD card) or expanded analog sensing capability. | Choose when additional serial peripheral bandwidth or higher channel-count ADC is required without increasing package size. |
Compared with LPC1112FHN33/102, the LPC1112FHN33/202K offers larger SRAM and safety-enhancing windowed WDT; compared with LPC1112FHN33/203, it trades one SPI and three ADC channels for lower cost and identical core/peripheral feature set for basic control tasks.
Availability
LPC1112FHN33/202K is available at Aetrix Electronics and suitable for lighting control, alarm systems, and eMetering applications requiring stable component supply, long-term lifecycle support, and RoHS-compliant sourcing.
Supply support for LPC1112FHN33/202K includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC111x product line targets cost-sensitive, low-power embedded applications - designed to replace 8/16-bit MCUs with ARM-based performance, simplified toolchain integration, and energy-efficient operation in space-constrained designs.
FAQ
What is the maximum operating frequency of the LPC1112FHN33/202K?
The LPC1112FHN33/202K operates at a maximum CPU frequency of 50 MHz. This speed is achievable using either the internal 12 MHz RC oscillator (trimmed to ±1 % accuracy) or an external crystal oscillator (1–25 MHz) with PLL multiplication. The 50 MHz rating applies under specified voltage (1.8–3.6 V) and temperature (−40 °C to +85 °C) conditions per the official NXP datasheet Rev. 9.2.
Does the LPC1112FHN33/202K support Serial Wire Debug (SWD)?
Yes, the LPC1112FHN33/202K supports Serial Wire Debug (SWD) via dedicated SWDIO (PIO1_3) and SWCLK (PIO0_10) pins. This two-pin debug interface enables full programming, breakpoint setting, and real-time variable inspection without requiring JTAG pins, simplifying PCB layout and reducing pin count overhead in the LPC1112FHN33/202K design.
How much flash and SRAM does the LPC1112FHN33/202K include?
The LPC1112FHN33/202K integrates 16 kB of on-chip flash memory and 4 kB of SRAM. Flash is used for program storage and supports In-System Programming (ISP) and In-Application Programming (IAP) via the on-chip bootloader. SRAM serves as runtime data memory, stack, and heap space - sufficient for bare-metal or lightweight RTOS implementations in the LPC1112FHN33/202K.
What distinguishes the LPC1112FHN33/202K from the LPC1112FHN33/102?
The LPC1112FHN33/202K belongs to the LPC1100L series and includes power profiles in boot ROM and a windowed watchdog timer - features absent in the LPC1112FHN33/102 (LPC1100 series). It also provides 4 kB SRAM versus 2 kB in the /102 variant, enabling more complex firmware execution within the same HVQFN33 package and pinout of the LPC1112FHN33/202K.
Which communication interfaces are available on the LPC1112FHN33/202K?
The LPC1112FHN33/202K provides one UART with RS-485 support, one I²C-bus interface compliant with Fast-mode Plus (1 Mbit/s), and one SPI controller with SSP features. It does not include a second SPI interface - that feature is exclusive to LPC1100XL-series variants like the LPC1112FHN33/203. All interfaces are accessible on the 33-pin HVQFN33 package of the LPC1112FHN33/202K.
LPC1112FHN33/202K Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VQFN Exposed Pad
- Series:
- LPC1100L
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 28
- Program Memory Size:
- 16KB (16K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 2K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 8x10b SAR
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1112FHN33/202K FAQ
1.How can I place an order for LPC1112FHN33/202K through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1112FHN33/202K on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1112FHN33/202K reliable?
The price and inventory of LPC1112FHN33/202K are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1112FHN33/202K is usually 5 days.
3.What payment methods are accepted for LPC1112FHN33/202K?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1112FHN33/202K transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC1112FHN33/202K?
LPC1112FHN33/202K orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1112FHN33/202K order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1112FHN33/202K?
For technical support, including LPC1112FHN33/202K datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1112FHN33/202K requirements.
6.How does Aetrix verify that LPC1112FHN33/202K is sourced from the original manufacturer or authorized distributors?
All LPC1112FHN33/202K products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1112FHN33/202K meets industry standards.
7.What is the process for return or replacement of LPC1112FHN33/202K?
All LPC1112FHN33/202K units undergo pre-shipment inspection (PSI). If there is an issue with LPC1112FHN33/202K, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1112FHN33/202K part is unused and in its original packaging.
Return procedure for LPC1112FHN33/202K:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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