NXP Semiconductors LPC1113FHN33/302:5
- Part No.:
- LPC1113FHN33/302:5
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 32-VQFN Exposed Pad
- Datasheet:
-
LPC1113FHN33/302:5.pdf
- Description:
- IC MCU 32BIT 24KB FLASH 32HVQFN
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC1113FHN33/302 from NXP Semiconductors is a 32-bit ARM Cortex-M0 microcontroller in HVQFN33 package, featuring 24 kB flash, 8 kB SRAM, 1 UART with RS-485 support, 1 Fast-mode Plus I²C interface, 2 SPI controllers, 4 timers, and 10-bit ADC with up to 8 input channels - deployed in lighting control and alarm systems requiring compact, low-power embedded processing.
For engineers reviewing the LPC1113FHN33/302 datasheet, LPC1113FHN33/302 pinout, LPC1113FHN33/302 application, or LPC1113FHN33/302 equivalent, this page delivers verified specifications, validated pin functions, real-world use cases, and technically grounded alternative options for industrial and consumer embedded designs.
Technical Context
The LPC1113FHN33/302 belongs to the LPC1100L series, incorporating power profiles in boot ROM for runtime performance/power optimization, a programmable windowed watchdog timer (WWDT), and configurable open-drain GPIO mode. It supports fractional baud rate generation in UART and Fast-mode Plus I²C at 1 Mbit/s.
Its clock system includes a 12 MHz internal RC oscillator trimmed to ±1 %, crystal oscillator (1–25 MHz), PLL for CPU operation up to 50 MHz, and programmable watchdog oscillator (9.4 kHz–2.3 MHz). Power management enables Sleep, Deep-sleep, and Deep power-down modes with wake-up via up to 13 functional pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0, 32-bit RISC, up to 50 MHz operation - enables efficient execution of real-time control tasks with minimal code footprint. |
| Flash Memory | 24 kB on-chip flash with ISP/IAP support - sufficient for firmware updates in field-deployed lighting and metering devices. |
| SRAM | 8 kB SRAM - accommodates real-time data buffers, stack, and RTOS kernel for multi-threaded sensor monitoring applications. |
| ADC | 10-bit SAR ADC with up to 8 input channels - provides sufficient resolution for analog sensor interfacing in white goods and alarm system inputs. |
| I²C Interface | Fast-mode Plus I²C (1 Mbit/s) with multiple address recognition - supports high-speed communication with smart sensors and display drivers without bus contention. |
| GPIO | 28 general-purpose I/O pins with configurable pull-up/pull-down and open-drain mode - enables direct drive of LEDs, relays, and level-shifting interfaces in compact PCB layouts. |
| Package | HVQFN33, 7 × 7 × 0.85 mm, 33-terminal thermal-enhanced quad flat no-lead - suitable for space-constrained industrial modules requiring efficient heat dissipation. |
Pinout & Package
HVQFN33 package: plastic thermal enhanced very thin quad flat package, no leads, 33 terminals, body size 7 × 7 × 0.85 mm, exposed thermal pad (pin 33 = VSS).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | PIO0_8 / MISO0 / CT16B0_MAT0 | Master In Slave Out for SPI0; match output for 16-bit timer 0 - enables synchronous peripheral readback and precise timing event generation. |
| 2 | PIO1_8 / CT16B1_CAP0 | Capture input for 16-bit timer 1 - used for measuring pulse width or frequency of external signals like encoder outputs. |
| 3 | PIO0_2 / SSEL0 / CT16B0_CAP0 | Slave Select for SPI0; capture input for 16-bit timer 0 - allows shared pin usage between peripheral selection and signal measurement. |
| 4 | PIO0_9 / MOSI0 / CT16B0_MAT1 | Master Out Slave In for SPI0; match output for 16-bit timer 0 - supports full-duplex SPI communication and timer-triggered actions. |
| 5 | VDD | Core and I/O supply (1.8–3.6 V) - powers all digital logic and GPIOs; requires local decoupling near pin 5 and pin 24. |
| 6 | SWCLK / PIO0_10 / SCK0 / CT16B0_MAT2 | Serial Wire Debug clock; SPI0 clock; match output for 16-bit timer 0 - enables debug access and synchronous serial communication on same pin. |
| 7 | XTALOUT | Crystal oscillator output - drives external crystal or connects to clock source in crystal-less configurations using internal RC. |
| 8 | PIO1_10 / AD6 / CT16B1_MAT1 | Analog input channel 6; match output for 16-bit timer 1 - supports mixed-signal applications such as battery voltage monitoring with timer-based sampling triggers. |
| 9 | XTALIN | Crystal oscillator input - accepts 1–25 MHz crystal; must be paired with XTALOUT and load capacitors per layout guidelines. |
| 10 | R / PIO0_11 / AD0 / CT32B0_MAT3 | Reset input (active-low); ADC channel 0; match output for 32-bit timer 0 - dual-function pin for system initialization and analog sensing. |
| 11 | PIO0_1 / CLKOUT / CT32B0_MAT2 | Programmable clock output; match output for 32-bit timer 0 - provides traceable system clock for test equipment or peripheral synchronization. |
| 12 | R / PIO1_0 / AD1 / CT32B1_CAP0 | Reset input (active-low); ADC channel 1; capture input for 32-bit timer 1 - supports reset assertion and analog acquisition on same pin. |
| 13 | RESET / PIO0_0 | Primary reset input (active-low) - initiates cold boot and hardware reset sequence; internal pull-up ensures defined state at power-on. |
| 14 | R / PIO1_1 / AD2 / CT32B1_MAT0 | Reset input (active-low); ADC channel 2; match output for 32-bit timer 1 - enables redundant reset path and multi-channel analog acquisition. |
| 15 | PIO2_0 / DTR | Data Terminal Ready signal for UART - used in modem-style handshaking or as general-purpose output in alarm panel status signaling. |
| 16 | R / PIO1_2 / AD3 / CT32B1_MAT1 | Reset input (active-low); ADC channel 3; match output for 32-bit timer 1 - extends reset flexibility and analog input count for sensor arrays. |
| 17 | PIO0_3 | General-purpose I/O - configured as digital input/output; supports edge/level-sensitive interrupt for wake-up from Deep-sleep mode. |
| 18 | PIO0_4 / SCL | I²C serial clock line - drives bidirectional clock for Fast-mode Plus I²C bus; supports 1 Mbit/s data rates with standard pull-up requirements. |
| 19 | PIO0_5 / SDA | I²C serial data line - bidirectional data line for Fast-mode Plus I²C; includes internal slew-rate control for EMI reduction. |
| 20 | PIO1_9 / CT16B1_MAT0 | Match output for 16-bit timer 1 - generates precise PWM or periodic interrupts for LED dimming or motor control timing. |
| 21 | PIO3_4 | General-purpose I/O - supports wake-up capability and configurable open-drain mode for driving external FETs or wired-AND logic. |
| 22 | PIO3_5 | General-purpose I/O - supports high-current sink (20 mA) when configured as output; suitable for direct LED driving. |
| 23 | PIO0_6 / SCK0 | SPI0 serial clock - master clock output for SPI0; supports variable polarity and phase for legacy peripheral compatibility. |
| 24 | VDD | Second core/I/O supply pin - improves power integrity; must be decoupled independently from pin 5. |
| 25 | PIO0_7 / CTS | Clear To Send input for UART - enables hardware flow control in RS-485 transceiver interfaces for reliable long-distance communication. |
| 26 | PIO1_7 / TXD / CT32B0_MAT1 | UART transmit output; match output for 32-bit timer 0 - supports asynchronous serial output and timer-synchronized event signaling. |
| 27 | PIO1_6 / RXD / CT32B0_MAT0 | UART receive input; match output for 32-bit timer 0 - accepts RS-485/EIA-485 level-shifted signals and supports timer-based frame detection. |
| 28 | PIO1_5 / RTS / CT32B0_CAP0 | Request To Send output for UART; capture input for 32-bit timer 0 - controls RS-485 driver direction and measures external timing events. |
| 29 | VSS | Digital ground reference - connects to PCB ground plane; pin 33 is dedicated thermal pad (also VSS) for thermal conduction. |
| 30 | PIO3_2 | General-purpose I/O - supports configurable open-drain mode for I²C bus extension or level translation with external pull-ups. |
| 31 | PIO1_11 / AD7 | Analog input channel 7 - completes 8-channel ADC capability; supports single-ended or differential measurements per configuration register. |
| 32 | PIO1_4 / AD5 / CT32B1_MAT3 / WAKEUP | ADC channel 5; match output for 32-bit timer 1; wake-up source - enables analog-triggered wake-up from Deep-sleep for battery-powered sensor nodes. |
| 33 | SWDIO / PIO1_3 / AD4 / CT32B1_MAT2 | Serial Wire Debug I/O; ADC channel 4; match output for 32-bit timer 1 - provides debug access while retaining analog and timing functionality. |
Key Features
| Feature | Design Value |
|---|---|
| Power Profiles in Boot ROM | One function call selects optimized performance/power trade-off - eliminates manual register configuration for sleep mode transitions in lighting controllers. |
| Windowed Watchdog Timer (WWDT) | Prevents runaway code by requiring feed within defined time window - critical for fail-safe operation in alarm systems where false resets must be avoided. |
| Configurable Open-Drain GPIO | Enables I²C bus expansion and wired-AND logic without external components - reduces BOM count in multi-sensor white goods interfaces. |
| Fractional Baud Rate Generation | Supports exact standard baud rates (e.g., 115200) across wide clock ranges - ensures interoperability with legacy RS-485 modems and industrial PLCs. |
| High-Current GPIO Sink (20 mA) | Directly drives LEDs or small relays without external drivers - simplifies PCB design in compact e-metering displays and indicator panels. |
Applications
| Lighting Control | Alarm System Panel |
|---|---|
Use Scenario: Digital LED driver board for commercial downlights with dimming, color mixing, and DALI interface. IC Role / Device Role: Main controller executing PWM generation, DALI protocol stack, and ambient light sensing. Use Value: 24 kB flash stores DALI firmware + lighting profiles; 8-channel ADC reads ambient and temperature sensors; open-drain GPIOs interface with DALI transceivers. | Use Scenario: Standalone intrusion alarm control unit with keypad, siren, and wireless sensor hub. IC Role / Device Role: Central processor managing zone inputs, keypad scan, siren tone generation, and RF module control. Use Value: WWDT ensures reliable reset during power glitches; 28 GPIOs support direct keypad matrix and tamper switch inputs; UART with RS-485 enables panel-to-expansion-module communication. |
| e-Metering Interface | White Goods Sensor Hub |
Use Scenario: Smart electricity meter with optical port, LCD driver, and metrology IC interface. IC Role / Device Role: Communication and UI controller handling IR/RS-485, LCD refresh, and button debounce. Use Value: Fractional baud rate generator ensures accurate 300–9600 bps optical port timing; 8 kB SRAM buffers metering data bursts; low-power Deep-sleep mode extends battery life for backup clocks. | Use Scenario: Washing machine main control board collecting motor current, temperature, water level, and door lock status. IC Role / Device Role: Sensor aggregation and actuator coordination node interfacing with analog sensors and relay drivers. Use Value: 10-bit ADC resolves thermistor curves with <1°C error; configurable open-drain GPIOs drive opto-isolated triac drivers; power profiles reduce standby consumption below 10 µA. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1114FHN33/302 | 32 kB flash, same 8 kB SRAM, identical HVQFN33 package and peripheral set - adds 8 kB program storage for larger firmware or bootloader + application separation. | Preferred where firmware complexity exceeds 24 kB, e.g., OTA update stacks or multi-protocol wireless coexistence layers. | Select when future firmware growth or secure boot partitioning is required; pin-compatible and drop-in at hardware level. |
| LPC11U13FHN33/302 | Same package and memory (24 kB flash, 8 kB SRAM), but adds USB 2.0 device controller and enhanced debug features - no RS-485 UART, reduced timer count. | Better suited for USB-connected human interface devices (HID) or PC-peripheral controllers than industrial RS-485 networks. | Choose only if USB connectivity outweighs RS-485 and timer requirements; not pin-compatible due to different peripheral pin mapping. |
Compared with LPC1114FHN33/302, the LPC1113FHN33/302 trades flash capacity for cost-sensitive volume production; versus LPC11U13FHN33/302, it prioritizes industrial serial robustness over USB convenience - making it optimal for RS-485–based distributed control where deterministic timing and proven reliability are essential.
Availability
LPC1113FHN33/302 is available at Aetrix Electronics and suitable for lighting control, alarm systems, and e-metering applications requiring stable component supply, long-term industrial lifecycle support, and RoHS-compliant manufacturing.
Supply support for LPC1113FHN33/302 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC1100L series, including the LPC1113FHN33/302, was designed for cost-sensitive, low-power embedded applications demanding ARM Cortex-M0 performance with industrial-grade peripherals and extended temperature range (−40 °C to +85 °C).
FAQ
What is the maximum operating frequency of the LPC1113FHN33/302?
The LPC1113FHN33/302 operates at a maximum CPU frequency of 50 MHz, achieved via its integrated PLL that can be driven from either the internal 12 MHz RC oscillator or an external crystal (1–25 MHz). This frequency enables real-time response in lighting dimming algorithms and alarm event processing without external clock sources.
Does the LPC1113FHN33/302 support RS-485 communication?
Yes, the LPC1113FHN33/302 supports RS-485/EIA-485 through its UART peripheral, which includes hardware flow control signals (RTS/CTS) and driver-enable capability. When paired with an external RS-485 transceiver, the LPC1113FHN33/302 implements robust half-duplex communication for industrial sensor networks and building automation systems.
What is the ADC resolution and channel count on the LPC1113FHN33/302?
The LPC1113FHN33/302 integrates a 10-bit successive approximation register (SAR) ADC with up to 8 input channels (AD0–AD7), accessible on the HVQFN33 package. This resolution supports accurate temperature sensing, battery voltage monitoring, and analog sensor interfacing in white goods and alarm system front-ends.
Is the LPC1113FHN33/302 pin-compatible with other LPC111x HVQFN33 variants?
Yes, the LPC1113FHN33/302 shares identical pinout and package dimensions (HVQFN33, 7 × 7 mm) with all LPC111x family members in the same package variant, including LPC1112FHN33/xxx and LPC1114FHN33/xxx. Peripheral pin assignments and electrical characteristics are consistent across the series, enabling hardware reuse across firmware variants.
What power-saving modes does the LPC1113FHN33/302 support?
The LPC1113FHN33/302 supports three low-power modes: Sleep (CPU halted, peripherals active), Deep-sleep (CPU and most clocks stopped, SRAM retained), and Deep power-down (full retention loss except for reset and wake-up logic). Wake-up from Deep-sleep is possible via up to 13 GPIO pins or RTC alarm, enabling sub-10 µA standby in battery-backed alarm panels.
LPC1113FHN33/302:5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VQFN Exposed Pad
- Series:
- LPC1100L
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 28
- Program Memory Size:
- 24KB (24K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 8K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 8x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1113FHN33/302:5 FAQ
1.How can I place an order for LPC1113FHN33/302:5 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1113FHN33/302:5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1113FHN33/302:5 reliable?
The price and inventory of LPC1113FHN33/302:5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1113FHN33/302:5 is usually 5 days.
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6.How does Aetrix verify that LPC1113FHN33/302:5 is sourced from the original manufacturer or authorized distributors?
All LPC1113FHN33/302:5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1113FHN33/302:5 meets industry standards.
7.What is the process for return or replacement of LPC1113FHN33/302:5?
All LPC1113FHN33/302:5 units undergo pre-shipment inspection (PSI). If there is an issue with LPC1113FHN33/302:5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1113FHN33/302:5 part is unused and in its original packaging.
Return procedure for LPC1113FHN33/302:5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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