My Inquiry
My Account
NXP Semiconductors LPC1114FHN33/202,5
- Part No.:
- LPC1114FHN33/202,5
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 32-VQFN Exposed Pad
- Datasheet:
-
LPC1114FHN33/202,5.pdf
- Description:
- IC MCU 32BIT 32KB FLASH 32HVQFN
- Quantity:
- Payment:
- Shipping:
Inventory:2,927
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC1114FHN33/202 from NXP Semiconductors is an ARM Cortex-M0 32-bit microcontroller in a 33-terminal HVQFN package, operating up to 50 MHz with 32 kB flash, 4 kB SRAM, one UART with RS-485 support, one I²C-bus interface (Fast-mode Plus), and up to 28 GPIO pins - deployed in lighting control and alarm systems requiring compact, low-power embedded processing.
For engineers reviewing the LPC1114FHN33/202 datasheet, LPC1114FHN33/202 pinout, LPC1114FHN33/202 application, or LPC1114FHN33/202 equivalent, this page delivers verified technical context, package-specific pin functions, power profile configuration, ADC input channel mapping, and validated alternative options for industrial firmware development and BOM optimization.
Technical Context
The LPC1114FHN33/202 implements the ARM Cortex-M0 core with NVIC and system tick timer, supporting Serial Wire Debug and non-maskable interrupt routing. Its clock system integrates a 12 MHz ±1 % internal RC oscillator, crystal oscillator (1–25 MHz), programmable watchdog oscillator (9.4 kHz–2.3 MHz), and PLL for CPU operation at full 50 MHz without external high-frequency crystals.
It belongs to the LPC1100L series, featuring power profiles in boot ROM for runtime performance/power trade-off selection, windowed watchdog timer, configurable open-drain GPIO mode, and brownout detection with four programmable thresholds - all enabled via dedicated system control registers and PMU hardware.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0, 32-bit RISC, supports Thumb-2 instruction set for compact code size vs. 8/16-bit MCUs. |
| Max Clock Frequency | 50 MHz - achieved via PLL from internal RC or crystal source, enabling real-time response in sensor polling loops. |
| Flash Memory | 32 kB - sufficient for bootloader + application firmware with IAP capability for field updates without external programmer. |
| SRAM | 4 kB - supports moderate stack depth, RTOS task contexts, and buffer storage for UART/I²C transaction queues. |
| ADC | 10-bit SAR with 8-channel multiplexing - enables simultaneous monitoring of temperature, voltage, and current sensors in white goods. |
| I/O Pins | 28 GPIO - includes edge/level-sensitive interrupt capability on all pins, critical for keypad scanning and tamper detection in alarm systems. |
| Serial Interfaces | 1 UART (RS-485 capable), 1 I²C (Fast-mode Plus, 1 Mbit/s), 1 SPI - supports multi-drop industrial bus communication and sensor hub connectivity. |
| Power Supply | 1.8 V to 3.6 V single supply - compatible with Li-ion battery-backed systems and standard 3.3 V logic rails. |
Pinout & Package
HVQFN33 package: plastic thermal-enhanced very thin quad flat package, no leads, 33 terminals, body size 7 × 7 × 0.85 mm, exposed thermal pad (pin 33 = VSS), RoHS-compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | PIO0_8 / MISO0 / CT16B0_MAT0 | SPI0 master-in-slave-out data line or 16-bit timer match output 0 - shared function requires software configuration. |
| 2 | PIO1_8 / CT16B1_CAP0 | GPIO or 16-bit timer 1 capture input - used for pulse-width measurement in motor control feedback. |
| 3 | PIO0_2 / SSEL0 / CT16B0_CAP0 | SPI0 slave select or 16-bit timer 0 capture input - dual role supports flexible peripheral sharing. |
| 4 | PIO0_9 / MOSI0 / CT16B0_MAT1 | SPI0 master-out-slave-in data line or 16-bit timer match output 1 - essential for sensor register writes. |
| 5 | VDD | Core and I/O power supply - must be decoupled with 100 nF ceramic capacitor near pin. |
| 6 | SWCLK / PIO0_10 / SCK0 / CT16B0_MAT2 | JTAG/SWD clock input or SPI0 clock - primary debug interface pin; conflicts with SPI0 use. |
| 7 | XTALOUT | Crystal oscillator output - drives external crystal when using crystal-based clock source. |
| 8 | PIO1_10 / AD6 / CT16B1_MAT1 | Analog input channel 6 or 16-bit timer 1 match output - enables analog sensing with timer-synchronized sampling. |
| 9 | XTALIN | Crystal oscillator input - connects to one terminal of external 1–25 MHz crystal. |
| 10 | R / PIO0_11 / AD0 / CT32B0_MAT3 | Reset input (active-low) or ADC channel 0 or 32-bit timer match output 3 - reset priority overrides other functions. |
| 11 | PIO0_1 / CLKOUT / CT32B0_MAT2 | Programmable clock output or 32-bit timer match output 2 - useful for driving external logic or test equipment. |
| 12 | R / PIO1_0 / AD1 / CT32B1_CAP0 | Reset input (active-low) or ADC channel 1 or 32-bit timer 1 capture input - alternate reset pin for redundancy. |
| 13 | RESET / PIO0_0 | Primary reset input - asserted low to initialize core, peripherals, and memory subsystems. |
| 14 | R / PIO1_1 / AD2 / CT32B1_MAT0 | Reset input (active-low) or ADC channel 2 or 32-bit timer 1 match output 0 - secondary reset with analog/timer capability. |
| 15 | PIO2_0 / DTR | Data terminal ready signal or GPIO - used in UART modem control handshaking or general-purpose flag signaling. |
| 16 | R / PIO1_2 / AD3 / CT32B1_MAT1 | Reset input (active-low) or ADC channel 3 or 32-bit timer 1 match output 1 - third reset option with mixed-signal flexibility. |
| 17 | PIO0_3 | General-purpose I/O - supports interrupt-on-change for wake-up from Deep-sleep mode. |
| 18 | PIO0_4 / SCL | I²C serial clock line - bidirectional, open-drain, requires external pull-up resistor. |
| 19 | PIO0_5 / SDA | I²C serial data line - bidirectional, open-drain, shares same pull-up as SCL. |
| 20 | PIO1_9 / CT16B1_MAT0 | 16-bit timer 1 match output 0 or GPIO - drives LED dimming PWM or relay timing signals. |
| 21 | PIO3_4 | General-purpose I/O - supports wake-up interrupt and configurable pull-up/pull-down resistors. |
| 22 | PIO3_5 | General-purpose I/O - usable as RTS/CTS flow control in UART or as status indicator output. |
| 23 | PIO0_6 / SCK0 | SPI0 clock line - master-generated clock for synchronous data transfer with sensors or displays. |
| 24 | PIO0_7 / CTS | UART clear-to-send input - hardware flow control signal for reliable RS-485 transmission. |
| 25 | PIO1_7 / TXD / CT32B0_MAT1 | UART transmit data or 32-bit timer match output 1 - primary serial output for diagnostics or telemetry. |
| 26 | PIO1_6 / RXD / CT32B0_MAT0 | UART receive data or 32-bit timer match output 0 - captures incoming commands or sensor data streams. |
| 27 | PIO1_5 / RTS / CT32B0_CAP0 | UART request-to-send output or 32-bit timer capture input - controls transceiver direction in half-duplex RS-485. |
| 28 | VDD | Second core/I/O power supply pin - improves power integrity and reduces noise coupling. |
| 29 | PIO3_2 | General-purpose I/O - supports high-current sink (20 mA) when configured as output. |
| 30 | PIO1_11 / AD7 | Analog input channel 7 - extends ADC coverage to 8 channels for multi-sensor applications. |
| 31 | PIO1_4 / AD5 / CT32B1_MAT3 / WAKEUP | ADC channel 5, timer match output, or wake-up source - enables low-power sleep with event-triggered resume. |
| 32 | SWDIO / PIO1_3 / AD4 / CT32B1_MAT2 | SWD data I/O or ADC channel 4 or timer match output 2 - primary debug interface pin with analog backup. |
| 33 | VSS | Ground reference and thermal pad connection - must be soldered to PCB ground plane for thermal management. |
Key Features
| Feature | Design Value |
|---|---|
| Power Profiles in Boot ROM | Enables runtime selection between performance, low-power, and balanced modes via single API call - eliminates manual register tuning. |
| Windowed Watchdog Timer | Prevents runaway code by requiring service within defined time window - critical for fail-safe alarm system operation. |
| Configurable Open-Drain GPIO | Supports I²C bus compatibility and wired-AND logic without external components - reduces BOM count in sensor networks. |
| High-Current Sink on I²C Pins | 20 mA drive capability on SDA/SCL allows direct LED indication or level translation - avoids external drivers in status interfaces. |
| Brownout Detection with 4 Thresholds | Provides selectable voltage monitoring (e.g., 2.0 V, 2.4 V, 2.7 V, 3.0 V) for graceful shutdown or warning before supply collapse. |
| Wake-Up from Deep-Sleep via GPIO | 13 functional pins can trigger wake-up - enables ultra-low-power monitoring of door/window sensors in security systems. |
Applications
| Lighting Control | Alarm Systems |
|---|---|
Use Scenario: Dimmable LED driver with ambient light sensing and wireless command reception. IC Role / Device Role / Timing Role: Main controller executing PWM generation, ADC sampling, and UART command parsing. Use Value: 28 GPIO enable independent channel control; 10-bit ADC resolves lux-level changes; UART supports DALI or proprietary protocol. | Use Scenario: Intrusion detection panel with PIR motion sensors, door contact switches, and siren output. IC Role / Device Role / Timing Role: Central alarm processor managing sensor inputs, timing delay windows, and audible alert sequencing. Use Value: Windowed WDT ensures firmware integrity; wake-up GPIO handles contact interrupts; 32 kB flash stores multiple zone configurations. |
| eMetering | White Goods |
Use Scenario: Single-phase electricity meter with current/voltage sensing, tamper detection, and optical port communication. IC Role / Device Role / Timing Role: Metering MCU performing RMS calculations, pulse counting, and IR data transmission. Use Value: 10-bit ADC with 8-channel mux samples shunt/transformer outputs; UART supports IEC 62056-21 optical interface. | Use Scenario: Washing machine main control board managing motor speed, water level, temperature, and user interface. IC Role / Device Role / Timing Role: System-on-chip handling motor commutation timing, ADC-based thermistor readings, and button/keypad scanning. Use Value: 50 MHz Cortex-M0 executes PID loops in real time; 4 kB SRAM buffers sensor data; open-drain GPIO drives display segments directly. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC1114FBD48/302 | LQFP48 package (48 pins), 42 GPIO, identical flash/SRAM/peripherals but larger footprint and higher pin count. | Preferred where board space permits and >28 I/O required for expanded sensor or display interfaces. | Select when needing full 42 GPIO or LQFP rework compatibility; not drop-in due to package and pinout mismatch. |
| LPC1113FHN33/202 | 24 kB flash, same HVQFN33 package, identical power profiles and peripheral set except reduced program memory. | Suitable for simpler firmware with smaller code size, e.g., basic timer-based controllers without complex protocols. | Choose for cost-sensitive designs where 24 kB flash suffices and existing PCB layout can be reused. |
Compared with LPC1114FHN33/202, the LPC1114FBD48/302 offers more I/O and larger package for expandability, while the LPC1113FHN33/202 reduces flash capacity to lower cost - both retain identical power management, ADC, and serial interface capabilities for seamless firmware porting.
Availability
LPC1114FHN33/202 is available at Aetrix Electronics and suitable for lighting control, alarm systems, and eMetering requiring stable component supply, long-term production support, and RoHS-compliant packaging.
Supply support for LPC1114FHN33/202 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC111x family targets cost-sensitive 8/16-bit MCU replacement applications, emphasizing low power, small footprint, and integrated analog/digital peripherals for embedded control in resource-constrained environments.
FAQ
What is the maximum operating frequency of the LPC1114FHN33/202?
The LPC1114FHN33/202 operates at a maximum CPU frequency of 50 MHz. This speed is achieved using the on-chip PLL, which can be clocked from either the internal 12 MHz ±1 % RC oscillator or an external crystal (1–25 MHz). The 50 MHz rating is guaranteed across the full industrial temperature range (−40 °C to +85 °C) and 1.8–3.6 V supply, making it suitable for real-time control tasks in lighting and alarm systems where deterministic timing is required. The LPC1114FHN33/202 does not require an external high-frequency crystal to reach its rated speed.
Does the LPC1114FHN33/202 support in-application programming (IAP)?
Yes, the LPC1114FHN33/202 supports In-Application Programming (IAP) via its on-chip bootloader. This allows firmware updates to be performed while the device is running - for example, receiving new code over UART or I²C and writing it to flash without halting operation. IAP is enabled through dedicated ROM API calls and requires proper sector erase/write sequencing. The LPC1114FHN33/202 also supports In-System Programming (ISP) via UART using standard tools like Flash Magic. Both methods preserve the 32 kB flash integrity and are fully documented in the NXP UM10398 user manual.
What ADC resolution and channel count does the LPC1114FHN33/202 provide?
The LPC1114FHN33/202 integrates a 10-bit successive approximation register (SAR) ADC with multiplexing across up to 8 input channels (AD0–AD7), all accessible on the HVQFN33 package. It supports programmable sample rates, burst mode, and hardware trigger sources including timers and interrupts. The ADC achieves ±2 LSB integral nonlinearity and operates across the full 1.8–3.6 V supply range. Its 8-channel capability enables concurrent monitoring of multiple analog sensors - such as thermistors, potentiometers, or current shunts - in white goods and eMetering applications where the LPC1114FHN33/202 serves as the primary data acquisition node.
Is the LPC1114FHN33/202 pin-compatible with other LPC111x HVQFN33 variants?
Yes, the LPC1114FHN33/202 is pin-compatible with all other LPC111x devices in the HVQFN33 package (e.g., LPC1111FHN33/202, LPC1112FHN33/202, LPC1113FHN33/202), sharing identical pin numbering, electrical characteristics, and peripheral mappings. Differences lie solely in flash size, SRAM capacity, and feature enablement (e.g., power profiles, windowed WDT), all controlled by internal configuration bits and boot ROM. This allows hardware reuse across product tiers - for instance, designing one PCB that supports LPC1113FHN33/202 (24 kB flash) and LPC1114FHN33/202 (32 kB flash) without layout changes.
What debug interface does the LPC1114FHN33/202 support?
The LPC1114FHN33/202 supports Serial Wire Debug (SWD) using two dedicated pins: SWDIO (PIO1_3) and SWCLK (PIO0_10). It does not support JTAG. SWD provides full debug functionality - including halt/resume, register read/write, memory access, and breakpoint setting - using only these two wires plus ground. The interface is compatible with standard tools such as LPC-Link2, CMSIS-DAP debug probes, and IDEs including Keil MDK and SEGGER Embedded Studio. SWD remains active even in low-power modes, enabling debugging during Deep-sleep wake-up sequences - a key advantage for battery-powered alarm and metering applications using the LPC1114FHN33/202.
LPC1114FHN33/202,5 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 32-VQFN Exposed Pad
- Series:
- LPC1100L
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 28
- Program Memory Size:
- 32KB (32K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 4K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 8x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1114FHN33/202,5 FAQ
1.How can I place an order for LPC1114FHN33/202,5 through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1114FHN33/202,5 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1114FHN33/202,5 reliable?
The price and inventory of LPC1114FHN33/202,5 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1114FHN33/202,5 is usually 5 days.
3.What payment methods are accepted for LPC1114FHN33/202,5?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC1114FHN33/202,5 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC1114FHN33/202,5?
LPC1114FHN33/202,5 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC1114FHN33/202,5 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1114FHN33/202,5?
For technical support, including LPC1114FHN33/202,5 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1114FHN33/202,5 requirements.
6.How does Aetrix verify that LPC1114FHN33/202,5 is sourced from the original manufacturer or authorized distributors?
All LPC1114FHN33/202,5 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1114FHN33/202,5 meets industry standards.
7.What is the process for return or replacement of LPC1114FHN33/202,5?
All LPC1114FHN33/202,5 units undergo pre-shipment inspection (PSI). If there is an issue with LPC1114FHN33/202,5, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1114FHN33/202,5 part is unused and in its original packaging.
Return procedure for LPC1114FHN33/202,5:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC1114FHN33/202,5 Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
