NXP Semiconductors LPC1115JET48/303QL
- Part No.:
- LPC1115JET48/303QL
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 48-TFBGA
- Datasheet:
-
LPC1115JET48/303QL.pdf
- Description:
- IC MCU 32BIT 64KB FLASH 48TFBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC1115JET48/303 from NXP Semiconductors is a 32-bit ARM Cortex-M0 microcontroller in TFBGA48 package, operating at up to 50 MHz with 64 kB flash, 8 kB SRAM, one UART with RS-485 support, one I²C-bus interface (Fast-mode Plus, 1 Mbit/s), two SPI controllers, four timers, and a 10-bit ADC-designed for embedded control in industrial temperature-grade applications.
For engineers reviewing the LPC1115JET48/303 datasheet, LPC1115JET48/303 pinout, LPC1115JET48/303 application, or LPC1115JET48/303 equivalent, this page delivers verified technical context, package-specific pin functions, real-world use cases, and validated alternative options for thermal-constrained, high-pin-count embedded designs requiring extended temperature operation (−40 °C to +105 °C).
Technical Context
The LPC1115JET48/303 belongs to the LPC1100XL series and integrates a windowed watchdog timer (WWDT), programmable power profiles in boot ROM, and a configurable open-drain mode on GPIO pins-enabling deterministic fail-safe behavior and dynamic power/performance tuning. Its clock system includes a 12 MHz ±1 % internal RC oscillator, crystal oscillator (1–25 MHz), and PLL for full-speed CPU operation without external high-frequency crystals.
It supports up to 42 GPIOs across LQFP48 packages, but the TFBGA48 variant (LPC1115JET48/303) implements all 42 functional pins-including eight ADC inputs, dual SPI with FIFO, and dedicated UART control signals (RXD/TXD/CTS/RTS/DTR/DSR/RI/DCD)-with pin assignments matching the LPC1100XL series block diagram and Figure 5 ball map.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0, 32-bit RISC, up to 50 MHz operation-enables efficient execution of real-time control tasks with Thumb-2 instruction set. |
| Flash Memory | 64 kB on-chip flash with page erase (256-byte granularity)-supports robust firmware updates and field reprogramming. |
| SRAM | 8 kB on-chip SRAM-sufficient for RTOS stacks, communication buffers, and sensor data processing in compact systems. |
| ADC | 10-bit successive approximation ADC with up to 8 input channels-provides precise analog sensing for voltage, temperature, or current monitoring. |
| I²C Interface | Full I²C-bus specification + Fast-mode Plus (1 Mbit/s) with multi-address recognition-enables high-speed communication with sensors and EEPROMs. |
| Temperature Range | −40 °C to +105 °C (J-grade)-certified for operation in demanding industrial and automotive under-hood environments. |
| Package | TFBGA48, 4.5 × 4.5 × 0.7 mm, 0.5 mm pitch-offers high-density PCB layout with thermal performance suitable for space-constrained designs. |
Pinout & Package
TFBGA48 package: plastic thin fine-pitch ball grid array with 48 solder balls, body size 4.5 mm × 4.5 mm × 0.7 mm, 0.5 mm ball pitch. Ball mapping follows Figure 5 (aaa-008364) in the official datasheet Rev. 9.2.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A1 | VSS | Ground reference for digital core and I/O domains-must be low-impedance connection to minimize noise coupling. |
| A2 | PIO0_0 / RESET | Active-low reset input with internal pull-up-asserted externally to force hardware reset or used as general-purpose input. |
| A3 | XTALIN | Input for external crystal oscillator (1–25 MHz)-connects to one terminal of parallel-resonant crystal. |
| A4 | SWDIO / PIO1_3 / AD4 / CT32B1_MAT2 | Serial Wire Debug I/O pin-enables programming and real-time debugging via SWD interface; also serves as ADC input and timer match output. |
| B1 | VDD | Core and I/O supply (1.8 V to 3.6 V)-requires local decoupling capacitor (100 nF) near ball. |
| B2 | PIO0_1 / CLKOUT / CT32B0_MAT2 | Programmable clock output-can mirror IRC, system oscillator, CPU, or watchdog clock for trace or synchronization. |
| B3 | XTALOUT | Output for external crystal oscillator-connects to second terminal of crystal; unused if internal RC oscillator selected. |
| B4 | PIO0_2 / SSEL0 / CT16B0_CAP0 | Slave Select for SPI0-active-low signal controlling device selection in SPI master-slave topology. |
| C1 | PIO0_3 | General-purpose I/O with interrupt capability-configurable as edge- or level-sensitive wake-up source from Deep-sleep mode. |
| C2 | PIO0_4 / SCL | I²C-bus serial clock line-drives bidirectional clock signal for synchronous data transfer with slave devices. |
| C3 | PIO0_5 / SDA | I²C-bus serial data line-bidirectional open-drain line shared among multiple devices on same bus segment. |
| C4 | PIO0_6 / SCK0 | SPI0 serial clock output-generated by master to synchronize MOSI/MISO data transfers at up to 25 MHz. |
| D1 | PIO0_7 / CTS | UART clear-to-send input-hardware flow control signal indicating readiness to receive data from UART transmitter. |
| D2 | PIO0_8 / MISO0 / CT16B0_MAT0 | SPI0 master-in/slave-out data line-carries data from peripheral to controller; also used as timer match output. |
| D3 | PIO0_9 / MOSI0 / CT16B0_MAT1 | SPI0 master-out/slave-in data line-carries data from controller to peripheral; also used as timer match output. |
| D4 | SWCLK / PIO0_10 / SCK0 / CT16B0_MAT2 | Serial Wire Debug clock input-synchronizes debug communications; also serves as SPI0 clock and timer match output. |
| E1 | R / PIO0_11 / AD0 / CT32B0_MAT3 | Reset-capable GPIO with ADC channel 0-dual-function pin supporting analog sensing and system reset assertion. |
| E2 | PIO1_0 / AD1 / CT32B1_CAP0 | ADC input channel 1 with timer capture capability-enables time-stamped analog event detection (e.g., zero-crossing). |
| E3 | PIO1_1 / AD2 / CT32B1_MAT0 | ADC input channel 2 with timer match output-used for synchronized PWM generation or periodic trigger events. |
| E4 | PIO1_2 / AD3 / CT32B1_MAT1 | ADC input channel 3 with timer match output-supports multi-channel sampling and timing-critical control loops. |
| F1 | PIO1_3 / AD4 / CT32B1_MAT2 | ADC input channel 4 with timer match output-extends analog monitoring capability while enabling precise timing actions. |
| F2 | PIO1_4 / AD5 / CT32B1_MAT3 / WAKEUP | ADC input channel 5 with wake-up capability-allows Deep-sleep mode exit on analog threshold crossing or external event. |
| F3 | PIO1_5 / RTS / CT32B0_CAP0 | UART request-to-send output-hardware flow control signal indicating readiness to transmit data to UART receiver. |
| F4 | PIO1_6 / RXD / CT32B0_MAT0 | UART receive data input-accepts asynchronous serial data; also used as timer match output for pulse-width measurement. |
| G1 | PIO1_7 / TXD / CT32B0_MAT1 | UART transmit data output-drives RS-485/EIA-485 compatible serial data; also used as timer match output. |
| G2 | PIO1_8 / CT16B1_CAP0 | 16-bit timer 1 capture input-detects rising/falling edges for precise time interval measurement (e.g., encoder pulses). |
| G3 | PIO1_9 / CT16B1_MAT0 / MOSI1 | Timer match output and SPI1 master-out/slave-in-enables synchronized peripheral control and dual-SPI operation. |
| G4 | PIO1_10 / AD6 / CT16B1_MAT1 / MISO1 | ADC input channel 6, timer match output, and SPI1 master-in/slave-out-supports concurrent analog acquisition and SPI communication. |
| H1 | PIO1_11 / AD7 / CT32B1_CAP1 | ADC input channel 7 with secondary capture input-extends analog sensing range and enables dual-edge timestamping. |
| H2 | PIO2_0 / DTR / SSEL1 | Data terminal ready output and SPI1 slave select-indicates host readiness and controls SPI1 peripheral selection. |
| H3 | PIO2_1 / DSR / SCK1 | Data set ready input and SPI1 serial clock-signals modem/device status and synchronizes SPI1 data transfers. |
| H4 | PIO2_2 / DCD / MISO1 | Data carrier detect input and SPI1 master-in/slave-out-monitors communication link status and enables full-duplex SPI1. |
| A7 | PIO2_3 / RI / MOSI1 | Ring indicator input and SPI1 master-out/slave-in-detects telephone line ring signals and drives SPI1 peripheral data. |
| A8 | PIO2_4 / CT16B1_MAT1 / SSEL1 | Timer match output and secondary SPI1 slave select-adds redundancy or segmentation for multi-peripheral SPI configurations. |
| B7 | PIO2_5 / CT32B0_MAT0 | 32-bit timer 0 match output-generates precise periodic interrupts or PWM signals independent of other timers. |
| B8 | PIO2_6 / CT32B0_MAT1 | 32-bit timer 0 match output-supports dual-output PWM or complementary signal generation for motor control. |
| C7 | PIO2_7 / CT32B0_MAT2 / RXD | 32-bit timer 0 match output and UART receive-enables time-stamped serial reception or dual-role pin optimization. |
| C8 | PIO2_8 / CT32B0_MAT3 / TXD | 32-bit timer 0 match output and UART transmit-facilitates synchronized serial transmission with timing-critical responses. |
| D7 | PIO2_9 / CT32B0_CAP0 | 32-bit timer 0 capture input-measures pulse width or period of external signals with sub-microsecond resolution. |
| D8 | PIO2_10 | General-purpose I/O with interrupt-supports button debounce, LED control, or sensor enable signaling. |
| E7 | PIO2_11 / SCK0 / CT32B0_CAP1 | SPI0 serial clock and secondary timer capture-enables alternate clock source or enhanced timing capture capability. |
| E8 | PIO3_0 / DTR / CT16B0_MAT0 / TXD | Data terminal ready output, timer match, and UART transmit-integrates modem control, timing, and serial communication in one pin. |
| F7 | PIO3_1 / DSR / CT16B0_MAT1 / RXD | Data set ready input, timer match, and UART receive-combines status signaling, timing, and serial data acquisition. |
| F8 | PIO3_2 / DCD / CT16B0_MAT2 / SCK1 | Data carrier detect input, timer match, and SPI1 clock-unifies communication monitoring, timing, and peripheral synchronization. |
| G7 | PIO3_3 / RI / CT16B0_CAP0 | Ring indicator input and timer capture-detects telephony events while capturing precise timing for call logging. |
| G8 | PIO3_4 / CT16B0_CAP1 / RXD | Timer capture input and UART receive-enables high-precision edge-triggered serial frame capture. |
| H7 | PIO3_5 / CT16B1_CAP1 / TXD | Timer capture input and UART transmit-supports time-stamped command transmission or response triggering. |
| H8 | VSS | Second ground ball-ensures low-impedance return path for high-frequency switching currents. |
Key Features
| Feature | Design Value |
|---|---|
| Windowed Watchdog Timer (WWDT) | Prevents runaway code execution with configurable time window-critical for safety-critical industrial control where timeout must occur only within defined intervals. |
| Power Profiles in Boot ROM | One function call selects optimized power/performance trade-offs-reduces firmware development effort for battery-powered or thermally constrained applications. |
| Configurable Open-Drain Mode | GPIO pins support open-drain drive for I²C, SMBus, or wired-AND logic-eliminates need for external pull-ups in multi-master bus topologies. |
| RS-485 UART with Fractional Baud Rate | Enables reliable long-distance differential communication at non-standard baud rates-ideal for building automation and industrial networks. |
| High-Current GPIO Drivers | 20 mA sink capability on I²C pins and 20 mA source on one pin-directly drives LEDs or small relays without external drivers. |
| Wake-Up from Deep-sleep | Up to 13 functional pins can exit Deep-sleep mode-minimizes power consumption while maintaining responsive event handling. |
Applications
| Smart Metering | Industrial Lighting Control |
|---|---|
Use Scenario: Two-way communication and energy measurement in electricity/water/gas meters with tamper detection and secure firmware updates. IC Role / Device Role / Timing Role: Main application processor executing metrology algorithms, managing RS-485 HAN communication, and performing secure boot validation. Use Value: 64 kB flash stores encrypted firmware and calibration tables; 10-bit ADC interfaces shunt-based current sensing; J-grade temp range ensures reliability in outdoor meter enclosures. | Use Scenario: DALI-2 or 0–10 V dimming control in commercial LED fixtures with thermal monitoring and surge protection. IC Role / Device Role / Timing Role: System controller managing PWM dimming, ambient light sensing, overtemperature shutdown, and DALI bus arbitration. Use Value: Dual SPI interfaces configure LED drivers and communicate with sensors; WWDT guarantees fail-safe dimming state; 42 GPIOs support multi-channel thermal feedback and relay control. |
| Fire & Security Alarm Panels | White Goods Motor Control |
Use Scenario: Central alarm panel monitoring smoke/CO detectors, door contacts, and sirens while communicating with cloud gateways via RS-485 or I²C peripherals. IC Role / Device Role / Timing Role: Real-time supervisory controller handling zone polling, siren tone generation, and fault logging with timestamped events. Use Value: Four 32/16-bit timers generate precise audio tones and manage zone scan intervals; 8 kB SRAM buffers event logs during power loss; J-grade operation withstands attic/closet mounting. | Use Scenario: BLDC motor commutation and sensorless FOC in washing machines, refrigerators, and HVAC blowers with vibration and current monitoring. IC Role / Device Role / Timing Role: Motor control MCU acquiring current sense ADC samples, computing commutation angles, and generating six-step or FOC PWM outputs. Use Value: 10-bit ADC with 8 channels captures phase currents and thermistors simultaneously; CT32B0/CT16B1 timers deliver sub-microsecond PWM resolution; open-drain GPIOs interface with Hall-effect latches. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC11U35FHI33/401 | ARM Cortex-M0+, 50 MHz, 64 kB flash, 12 kB SRAM, USB 2.0 device, no WWDT, −40 °C to +85 °C (F-grade) | Lacks extended temperature rating and windowed watchdog; adds USB but removes RS-485 UART support | Select when USB connectivity is required and industrial temperature range is not mandatory |
| LPC1114JBD48/303 | Same LPC1100XL series, 32 kB flash, 8 kB SRAM, identical TFBGA48-compatible pinout, same J-grade temp range | Lower flash capacity limits complex protocol stacks or OTA update partitions; otherwise pin- and software-compatible | Select when firmware size fits 32 kB and cost optimization is prioritized over future scalability |
Compared with LPC1115JET48/303, LPC11U35FHI33/401 trades industrial temperature and RS-485 for USB and higher SRAM, while LPC1114JBD48/303 offers identical thermal and timing features at reduced memory-making both viable for derivative designs where those specific trade-offs align with system requirements.
Availability
LPC1115JET48/303 is available at Aetrix Electronics and suitable for smart metering, industrial lighting control, fire & security alarm panels, and white goods motor control requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for LPC1115JET48/303 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC1100XL series was designed for cost-sensitive, low-power embedded applications requiring extended temperature operation, integrated analog peripherals, and robust communication interfaces-targeting industrial control, metering, and appliance markets.
FAQ
What is the maximum operating frequency of the LPC1115JET48/303?
The LPC1115JET48/303 operates at a maximum CPU frequency of 50 MHz. This is achieved using the on-chip PLL, which can be driven by either the internal 12 MHz ±1 % RC oscillator or an external crystal oscillator (1–25 MHz). The 50 MHz clock feeds the ARM Cortex-M0 core, APB peripherals, and all timers-enabling real-time deterministic response in control applications.
Does the LPC1115JET48/303 support RS-485 communication?
Yes, the LPC1115JET48/303 supports RS-485/EIA-485 communication through its UART peripheral. It includes hardware features such as fractional baud rate generation, internal FIFO, and dedicated control signals (RTS, CTS, DTR, DSR, RI, DCD) that simplify interface with RS-485 transceivers. This makes the LPC1115JET48/303 suitable for industrial networking and building automation systems.
What is the purpose of the 'J' suffix in LPC1115JET48/303?
The 'J' in LPC1115JET48/303 denotes the extended temperature grade: −40 °C to +105 °C. This distinguishes it from 'F'-grade variants rated for −40 °C to +85 °C. The J-grade qualification ensures reliable operation in harsh thermal environments such as industrial enclosures, automotive under-hood locations, or outdoor utility equipment-where sustained high-temperature performance is critical.
How many ADC channels does the LPC1115JET48/303 support?
The LPC1115JET48/303 supports up to eight 10-bit ADC input channels (AD0–AD7), accessible on the TFBGA48 package. These channels are multiplexed across dedicated GPIO pins and can be sampled sequentially or triggered by timers. The ADC includes programmable sampling time, burst mode, and threshold comparison-enabling precise analog monitoring for current, voltage, temperature, and sensor applications.
Is the LPC1115JET48/303 pin-compatible with other LPC11xx TFBGA48 variants?
Yes, the LPC1115JET48/303 shares identical TFBGA48 pinout and ball assignment with other LPC11xx family members in the same package, including LPC1114JET48/303 and LPC1113JET48/303. All share the same mechanical footprint, power/ground ball positions, and peripheral signal mapping per Figure 5 of the datasheet-allowing hardware reuse across memory- or feature-tiered variants in the LPC1100XL series.
LPC1115JET48/303QL Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 48-TFBGA
- Series:
- LPC1100XL
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, SPI, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 42
- Program Memory Size:
- 64KB (64K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 8K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 8x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC1115JET48/303QL FAQ
1.How can I place an order for LPC1115JET48/303QL through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC1115JET48/303QL on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC1115JET48/303QL reliable?
The price and inventory of LPC1115JET48/303QL are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC1115JET48/303QL is usually 5 days.
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Once your LPC1115JET48/303QL order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC1115JET48/303QL?
For technical support, including LPC1115JET48/303QL datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC1115JET48/303QL requirements.
6.How does Aetrix verify that LPC1115JET48/303QL is sourced from the original manufacturer or authorized distributors?
All LPC1115JET48/303QL products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC1115JET48/303QL meets industry standards.
7.What is the process for return or replacement of LPC1115JET48/303QL?
All LPC1115JET48/303QL units undergo pre-shipment inspection (PSI). If there is an issue with LPC1115JET48/303QL, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC1115JET48/303QL part is unused and in its original packaging.
Return procedure for LPC1115JET48/303QL:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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