My Inquiry
My Account
NXP Semiconductors LPC11E37FHI33/501E
- Part No.:
- LPC11E37FHI33/501E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
LPC11E37FHI33/501E.pdf
- Description:
- IC MCU 32BIT 128KB FLASH 64LQFP
- Quantity:
- Payment:
- Shipping:
Inventory:2,571
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC11E37FHI33/501E from NXP Semiconductors is a 32-bit ARM Cortex-M0 microcontroller in HVQFN33 (5×5 mm) package, operating up to 50 MHz with 128 kB flash, 12 kB SRAM, and 4 kB EEPROM. It integrates a 10-bit ADC (8 channels), USART with RS-485/smart card support, two SSP interfaces, Fast-mode Plus I²C (1 Mbit/s), four timers, and 26 GPIO pins - deployed in handheld scanners and industrial control systems.
For engineers reviewing the LPC11E37FHI33/501E datasheet, LPC11E37FHI33/501E pinout, LPC11E37FHI33/501E application, or LPC11E37FHI33/501E equivalent, key selection criteria include its HVQFN33 footprint, 26 GPIO count, 128 kB flash density, 50 MHz CPU clock, and RS-485-capable USART for robust industrial serial communication.
Technical Context
The LPC11E37FHI33/501E implements an ARM Cortex-M0 core with NVIC and system tick timer, supporting low-power operation via Sleep, Deep-sleep, Power-down, and Deep power-down modes managed by an integrated PMU. Its clock system combines a 1–25 MHz crystal oscillator, 12 MHz IRC, and PLL for flexible frequency synthesis up to 50 MHz.
Digital peripherals include four general-purpose timers (two 16-bit, two 32-bit), programmable Windowed WatchDog Timer with dedicated WDO, and GPIO interrupt grouping logic enabling pattern-matched wake-up. Analog functionality centers on a single 10-bit ADC with multiplexed inputs across eight pins.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0, 32-bit RISC architecture with Thumb-2 instruction set for compact code and deterministic real-time response. |
| Max Clock Frequency | 50 MHz - enables high-throughput data handling in serial protocols like RS-485 and synchronous USART mode. |
| Memory | 128 kB flash (sector/page erase), 12 kB SRAM (8+2+2 kB banks), 4 kB EEPROM (byte-erasable) - supports firmware updates and non-volatile parameter storage without external components. |
| ADC | 10-bit SAR ADC with 8 input channels - provides sufficient resolution for sensor interfacing in medical and industrial monitoring. |
| Serial Interfaces | 1 × USART (RS-485/9-bit/smart card), 2 × SSP (SPI-compatible), 1 × I²C-bus (Fast-mode Plus, 1 Mbit/s) - enables multi-protocol connectivity to sensors, displays, and legacy industrial buses. |
| GPIO | 26 configurable pins with pull-up/pull-down, repeater, open-drain modes; up to 8 support edge/level interrupts - suitable for direct button, LED, and discrete I/O control in space-constrained designs. |
| Package | HVQFN33 (5 × 5 × 0.85 mm) - thermally enhanced, leadless package optimized for compact PCB layouts and improved thermal dissipation in sealed enclosures. |
Pinout & Package
HVQFN33 (5×5 mm) package with 33 terminals, no leads, exposed thermal pad, and 0.5 mm pitch - designed for automated assembly and thermal reliability in industrial environments.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RESET/PIO0_0 | Reset input / GPIO | Active-low reset with 20 ns glitch filter; also debug select pin - requires external pull-up for Deep power-down wake-up compliance. |
| SWDIO/PIO0_15/AD4/CT32B1_MAT2 | Debug I/O / ADC / Timer | Primary SWD debug interface; shares pin with ADC input 4 and 32-bit timer match output - enables in-circuit debugging without dedicated debug header. |
| PIO0_18/RXD/CT32B0_MAT0 | USART receive / Timer | UART RX path for ISP and application use; doubles as 32-bit timer match output - supports bootloader activation and timing-critical signal generation. |
| PIO0_19/TXD/CT32B0_MAT1 | USART transmit / Timer | UART TX output with full modem handshake support; also 32-bit timer match output - essential for RS-485 half-duplex control and protocol timing. |
| PIO0_4/SCL/IOH_2 | I²C clock / I/O Handler | Open-drain SCL with Fast-mode Plus capability (1 Mbit/s); IOH_2 only on I/O Handler variants - not available on LPC11E37FHI33/501E per datasheet Table 2. |
| PIO0_5/SDA/IOH_3 | I²C data / I/O Handler | Open-drain SDA with Fast-mode Plus sink current; IOH_3 exclusive to LPC11E37HFBD64/401 - omitted on this variant. |
| VDD / VSS | Power / Ground | Single 3.3 V supply (1.8–3.6 V range); dual VDD/VSS pairs ensure stable core and I/O rail decoupling in noise-sensitive applications. |
Key Features
| Feature | Design Value |
|---|---|
| ARM Cortex-M0 + NVIC | Low-latency interrupt handling (<12 cycles) and deterministic execution ideal for real-time sensor polling and motor control loops. |
| EEPROM Integration | 4 kB on-chip byte-erasable EEPROM eliminates need for external serial EEPROM, reducing BOM cost and board area in calibration-critical devices. |
| Programmable Windowed Watchdog | Hardware-enforced safety mechanism with dedicated low-power WDO - prevents runaway code in unattended industrial equipment. |
| Multi-Mode Power Management | Four reduced-power states (Sleep to Deep power-down) with wake-up via GPIO or watchdog - extends battery life in portable scanners and handheld medical tools. |
| RS-485/Smart Card USART | Fractional baud rate generator and 9-bit mode enable interoperability with legacy industrial fieldbus nodes and secure identification readers. |
Applications
| Handheld Scanners | Industrial Control Panels |
|---|---|
Use Scenario: Battery-powered barcode scanner requiring low standby current and fast wake-up from button press. IC Role / Device Role / Timing Role: Main controller executing image capture, decode algorithms, and USB/UART host communication. Use Value: 26 GPIO support direct matrix keypad and status LED drive; Deep power-down mode achieves sub-1 µA sleep current for >1-year battery life. | Use Scenario: DIN-rail mounted HMI panel interfacing with PLCs via RS-485 and reading analog sensor inputs. IC Role / Device Role / Timing Role: Protocol bridge between touch interface, 10-bit ADC for temperature/pressure sensing, and isolated RS-485 transceiver. Use Value: Integrated 128 kB flash stores UI assets and firmware; hardware USART RS-485 mode eliminates external level-shifting logic. |
| Medical Diagnostic Tools | Consumer Peripherals |
Use Scenario: Portable pulse oximeter with analog front-end, OLED display, and Bluetooth UART bridge. IC Role / Device Role / Timing Role: Signal acquisition controller managing ADC sampling, SPI-driven display update, and UART-to-Bluetooth data forwarding. Use Value: 12 kB SRAM buffers waveform data; 10-bit ADC meets clinical accuracy requirements for SpO₂ calculation. | Use Scenario: Smart home gateway node aggregating Zigbee/Z-Wave sensor data and relaying via Wi-Fi UART interface. IC Role / Device Role / Timing Role: Co-processor handling protocol translation, secure boot, and low-level peripheral management offloaded from main SoC. Use Value: 4 kB EEPROM stores unique device keys; Fast-mode Plus I²C supports high-speed sensor fusion with environmental ICs. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC11E35FHI33/501 | 64 kB flash, same 26 GPIO, identical HVQFN33 package and peripheral set - lacks 64 kB additional flash capacity. | Suitable for simpler firmware with smaller memory footprint; not viable for OTA-upgradable feature-rich applications. | Select when firmware size remains under 64 kB and cost sensitivity outweighs future scalability needs. |
| LPC11U37FHI33/501 | Same package and pinout, but adds USB 2.0 device controller and enhanced ROM-based drivers - no USB PHY on LPC11E37FHI33/501. | Required where native USB HID or CDC-class connectivity replaces UART bridges in end-user devices. | Choose only if USB device functionality is mandatory; otherwise, LPC11E37FHI33/501 offers lower gate count and power for pure serial/embedded roles. |
Compared with LPC11E35FHI33/501, the LPC11E37FHI33/501 delivers 64 kB more flash for complex protocol stacks and firmware resilience, while LPC11U37FHI33/501 trades flash headroom for integrated USB - making the LPC11E37FHI33/501 optimal for RS-485-centric industrial edge nodes where USB is unnecessary.
Availability
LPC11E37FHI33/501E is available at Aetrix Electronics and suitable for handheld scanners, industrial control panels, and medical diagnostic tools requiring stable component supply across long production lifecycles.
Supply support for LPC11E37FHI33/501E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC11E3x product line targets cost-sensitive, low-power 32-bit MCU replacement of legacy 8/16-bit microcontrollers - emphasizing flash density, analog integration, and industrial serial interface support in compact packages.
FAQ
What is the maximum operating frequency of the LPC11E37FHI33/501E?
The LPC11E37FHI33/501E operates at a maximum CPU frequency of 50 MHz, achieved using either the internal 12 MHz IRC oscillator with PLL multiplication or an external 1–25 MHz crystal oscillator. This frequency enables deterministic real-time performance for RS-485 frame processing and ADC sampling at up to 400 kS/s in burst mode.
Does the LPC11E37FHI33/501E include on-chip EEPROM?
Yes, the LPC11E37FHI33/501E integrates 4 kB of on-chip EEPROM that is byte-erasable and byte-programmable, with API support in boot ROM. This eliminates the need for external EEPROM in applications requiring non-volatile storage of calibration data, device IDs, or user settings - directly accessible via standard I²C-like register writes.
How many GPIO pins does the LPC11E37FHI33/501E provide?
The LPC11E37FHI33/501E provides 26 general-purpose I/O pins in its HVQFN33 (5×5 mm) package. These support configurable pull-up/pull-down resistors, repeater mode, open-drain operation, and up to 8 pins can be configured as edge- or level-sensitive interrupt sources - sufficient for keypad scanning, LED driving, and discrete sensor interfacing in compact designs.
Is the LPC11E37FHI33/501E compatible with RS-485 communication?
Yes, the LPC11E37FHI33/501E's single USART supports RS-485 mode with 9-bit addressing, automatic direction control via RTS pin, and fractional baud rate generation - enabling reliable half-duplex communication over noisy industrial bus lines without external transceiver logic beyond the RS-485 driver IC.
What debug interfaces are supported by the LPC11E37FHI33/501E?
The LPC11E37FHI33/501E supports Serial Wire Debug (SWD) via SWDIO and SWCLK pins, and JTAG via TDI, TDO, TMS, TRST, and TCK - both fully compliant with ARM CoreSight standards. SWD is recommended for minimal pin count; JTAG remains available for boundary scan testing during PCB validation.
LPC11E37FHI33/501E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 64-LQFP
- Series:
- LPC11E3x
- Packaging:
- Tray
- Product Status:
- Obsolete
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, Microwire, SmartCard, SPI, SSP, UART/USART
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 28
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 12K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 8x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC11E37FHI33/501E FAQ
1.How can I place an order for LPC11E37FHI33/501E through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC11E37FHI33/501E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC11E37FHI33/501E reliable?
The price and inventory of LPC11E37FHI33/501E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC11E37FHI33/501E is usually 5 days.
3.What payment methods are accepted for LPC11E37FHI33/501E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC11E37FHI33/501E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC11E37FHI33/501E?
LPC11E37FHI33/501E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC11E37FHI33/501E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC11E37FHI33/501E?
For technical support, including LPC11E37FHI33/501E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC11E37FHI33/501E requirements.
6.How does Aetrix verify that LPC11E37FHI33/501E is sourced from the original manufacturer or authorized distributors?
All LPC11E37FHI33/501E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC11E37FHI33/501E meets industry standards.
7.What is the process for return or replacement of LPC11E37FHI33/501E?
All LPC11E37FHI33/501E units undergo pre-shipment inspection (PSI). If there is an issue with LPC11E37FHI33/501E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC11E37FHI33/501E part is unused and in its original packaging.
Return procedure for LPC11E37FHI33/501E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC11E37FHI33/501E Tags
-
ATTINY4-TSHR
Microchip Technology
-
ATTINY10-TSHR
Microchip Technology
-
ATTINY10-TS8R
Microchip Technology
-
ATTINY202-SSNR
Microchip Technology
-
ATTINY202-SSFR
Microchip Technology
-
ATTINY402-SSNR
Microchip Technology
-
PIC16F15213T-I/MF
Microchip Technology
-
PIC16F15213-E/MF
Microchip Technology
-
PIC10F200T-I/OT
Microchip Technology
-
ATTINY412-SSNR
Microchip Technology
-
PIC10F202T-I/OT
Microchip Technology
-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
