NXP Semiconductors LPC11E67JBD64E
- Part No.:
- LPC11E67JBD64E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
LPC11E67JBD64E.pdf
- Description:
- IC MCU 32BIT 128KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:297
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC11E67JBD64E from NXP Semiconductors is a 32-bit ARM Cortex-M0+ microcontroller operating at up to 50 MHz, featuring 128 KB flash, 4 KB EEPROM, 20 KB SRAM, a 12-bit ADC with 10 input channels, and 50 GPIO pins. It integrates two I²C interfaces (one Fast-mode Plus), five USARTs (four with shared fractional baud generator), two SSP controllers, and a configurable PWM/timer subsystem with SCTimer/PWM capability - deployed in GPS trackers and medical monitors requiring deterministic real-time control and low-power operation.
For engineers reviewing the LPC11E67JBD64E datasheet, LPC11E67JBD64E pinout, LPC11E67JBD64E application, or LPC11E67JBD64E equivalent, key selection criteria include its LQFP64 package with 64 leads, 10-channel 12-bit ADC sampling up to 2 Msamples/s, dual I²C support including Fast-mode Plus, and integrated PMU enabling Deep power-down mode with wake-up via PIO0_16.
Technical Context
The LPC11E67JBD64E implements an ARM Cortex-M0+ core with a two-stage pipeline, single-cycle I/O access, and built-in NVIC for deterministic interrupt handling. Its AHB multilayer matrix enables concurrent peripheral access, while the ROM API provides validated drivers for USART, I²C, DMA, and Flash IAP/ISP operations.
Peripherals are tightly coupled to the core via dedicated trigger muxes: the 12-bit ADC supports two independent conversion sequences with internal/external triggers; the SCTimer/PWM subsystem delivers up to 19 PWM outputs across six independent time bases; and the DMA engine features 16 channels with programmable input triggers tied to GPIO, timer, and ADC events.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+, r0p1 revision, 50 MHz max operation with single-cycle multiplier and fast I/O bus |
| Memory | 128 KB on-chip flash (page-erasable), 4 KB EEPROM, 20 KB SRAM (including two 2 KB blocks) |
| Analog | 12-bit ADC with 10 input channels, 2 Msamples/s max rate, two independent conversion sequences |
| Digital I/O | 50 GPIO pins with configurable pull-up/down, open-drain mode, glitch/digital filtering, and pin-interrupt capability |
| Serial Interfaces | Five USARTs (four with shared fractional baud generator, RS-485 mode), two I²C (one Fast-mode Plus), two SSP with DMA |
| Timers & PWM | SCTimer/PWM subsystem with 19 PWM outputs, six independent time bases; plus four standard timers (two 16-bit, two 32-bit) |
| Power Management | Integrated PMU supporting Sleep, Deep-sleep, Power-down, and Deep power-down modes; wake-up via GPIO or USART activity |
Pinout & Package
LPC11E67JBD64E is housed in a plastic LQFP64 package (SOT314-2), 10 × 10 × 1.4 mm body, with 64 leads and exposed pad for thermal dissipation. Pin functions are dynamically configurable via IOCON registers.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (RTCXIN) | RTC oscillator input | Accepts external 32.768 kHz crystal; required for RTC operation in always-on domain |
| 4 (RESET/PIO0_0) | Reset input / GPIO | Active-low reset with 20 ns glitch filter; also serves as debug select (HIGH = SWD, LOW = JTAG) |
| 39 (SWCLK/PIO0_10) | SWD clock / GPIO | Serial Wire Debug clock input; default SWD interface pin, configurable as GPIO |
| 50 (SWDIO/PIO0_15) | SWD data I/O / GPIO | Serial Wire Debug bidirectional data line; default debug interface, configurable as GPIO or ADC3 input |
| 51 (PIO0_16/WAKEUP) | GPIO / Deep power-down wake-up | Configurable GPIO with 20 ns glitch filter; must be pulled HIGH before entering Deep power-down, LOW to exit |
| 53 (VDDA) | Analog supply | 3.3 V analog power rail for ADC and internal reference; requires separate decoupling from digital VDD |
| 54 (VSSA) | Analog ground | Analog reference ground; must be connected to system ground with low-impedance path to minimize ADC noise |
| 63 (VBAT) | RTC backup supply | Connects to coin cell or supercap for RTC retention during main power loss; operates down to 1.1 V |
Key Features
| Feature | Design Value |
|---|---|
| ROM-based peripheral drivers | Pre-validated USART, I²C, DMA, and Flash IAP/ISP routines reduce firmware development time and ensure interoperability |
| Configurable SCTimer/PWM | State-configurable timer delivering up to 19 PWM outputs with six independent time bases for complex motor or lighting control |
| High-speed GPIO | Up to 50 GPIO pins connected directly to Cortex-M0+ I/O bus with single-cycle access and programmable filtering |
| Multi-trigger ADC | 12-bit ADC supports dual conversion sequences triggered by software, timers, or external events - enabling synchronized sensor sampling |
| Low-power Deep power-down | Sub-μA retention current with RTC active; wake-up in <10 μs via PIO0_16 or USART activity - critical for battery-powered trackers |
Applications
| GPS Tracker | Medical Monitor |
|---|---|
Use Scenario: Compact, battery-operated asset tracker logging position, motion, and environmental data at configurable intervals. IC Role / Device Role / Timing Role: Main system controller executing GNSS parsing, sensor fusion, and cellular/LPWAN transmission scheduling. Use Value: Deep power-down mode with RTC and wake-up on motion or timer enables multi-week battery life; 10-channel ADC supports simultaneous temperature, battery voltage, and biometric sensing. | Use Scenario: Portable patient vital sign monitor measuring ECG, SpO₂, and temperature with local display and BLE upload. IC Role / Device Role / Timing Role: Central MCU managing analog front-end acquisition, real-time signal processing, and wireless communication stack. Use Value: 12-bit ADC with 2 Msamples/s and dual conversion sequences captures high-fidelity biosignals; integrated PMU ensures compliance with IEC 62304 power safety requirements. |
| Car Radio Head Unit | Three-Phase E-Meter |
Use Scenario: Entry-level automotive infotainment head unit with AM/FM tuner, USB audio, and basic UI controls. IC Role / Device Role / Timing Role: Application processor handling user interface, audio codec interfacing, and peripheral management (I²C displays, SPI tuners). Use Value: Five USARTs support simultaneous connections to tuner, Bluetooth module, and diagnostic port; Fast-mode Plus I²C drives high-resolution touch displays without bus contention. | Use Scenario: DIN-rail mounted electricity meter measuring voltage, current, and power quality across three phases. IC Role / Device Role / Timing Role: Metering controller performing RMS calculations, harmonic analysis, and secure data logging. Use Value: CRC engine accelerates checksum validation of energy data; EEPROM retains calibration coefficients and tamper logs across 100k+ write cycles; -40 °C to +105 °C rating ensures field reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC11E68JBD64 | 256 KB flash, 36 KB SRAM, same peripherals and pinout | Higher memory headroom for OTA firmware updates or larger protocol stacks (e.g., Matter over Thread) | Select when future firmware growth or dual-bank update capability is required |
| LPC11U68JBD64 | USB 2.0 device controller, no EEPROM, identical flash/SRAM/peripherals otherwise | Enables direct USB HID or CDC device connectivity without external PHY | Select when native USB device functionality replaces UART-to-USB bridge ICs |
Compared with LPC11E67JBD64E, LPC11E68JBD64 offers double flash and SRAM for scalable firmware, while LPC11U68JBD64 trades EEPROM for USB device capability - both share identical LQFP64 pinout and peripheral sets, enabling board reuse where memory or interface priorities shift.
Availability
LPC11E67JBD64E is available at Aetrix Electronics and suitable for GPS trackers, medical monitors, car radio head units, and three-phase e-meters requiring stable component supply, long-term industrial lifecycle support, and guaranteed traceable sourcing.
Supply support for LPC11E67JBD64E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with headquarters in Eindhoven, Netherlands.
The LPC11E6x product line is designed for cost-sensitive, ultra-low-power embedded systems demanding high peripheral integration, robust real-time performance, and extended temperature operation - targeting metering, portable medical, and telematics applications.
FAQ
What is the maximum operating frequency of the LPC11E67JBD64E?
The LPC11E67JBD64E operates at a maximum CPU frequency of 50 MHz using the ARM Cortex-M0+ core. This speed is achievable with the internal PLL enabled and a stable clock source (e.g., 12 MHz IRC or external crystal). The core maintains single-cycle I/O access and deterministic interrupt latency even at full speed, making it suitable for time-critical sensor polling and communication tasks in the LPC11E67JBD64E.
Does the LPC11E67JBD64E include on-chip EEPROM, and what is its endurance?
Yes, the LPC11E67JBD64E integrates 4 KB of on-chip EEPROM with guaranteed endurance of at least 100,000 write/erase cycles and data retention of 10 years at 85 °C. This non-volatile memory is used for storing calibration data, device configuration, or usage logs without requiring external components - a key feature distinguishing the LPC11E67JBD64E from many competing Cortex-M0+ MCUs.
How many ADC input channels does the LPC11E67JBD64E support, and what is its sampling rate?
The LPC11E67JBD64E features a single 12-bit ADC with up to 10 input channels, as confirmed by Table 2 in the datasheet for the LQFP64 variant. It achieves a maximum sample rate of 2 Msamples/s and supports two independent conversion sequences triggered by software, timers, or external events - enabling synchronized multi-sensor acquisition critical in the LPC11E67JBD64E's target applications.
What debug interfaces are supported by the LPC11E67JBD64E?
The LPC11E67JBD64E supports Serial Wire Debug (SWD) as the primary debug interface, with SWDIO and SWCLK assigned to pins 50 and 39 respectively. JTAG boundary scan is also supported via TRST, TDI, TMS, and TDO on pins 46, 42, 43, and 45. SWD is enabled by default at reset; JTAG requires pulling RESET/PIO0_0 LOW during power-up - both protocols are fully functional in the LPC11E67JBD64E.
Is the LPC11E67JBD64E pin-compatible with other members of the LPC11E6x family?
Yes, the LPC11E67JBD64E shares identical pinout and footprint with other LQFP64 variants in the LPC11E6x family, including LPC11E66JBD64, LPC11E68JBD64, and LPC11U68JBD64. All use SOT314-2 packaging with matching signal assignments, power, and ground pin locations - allowing hardware design reuse across memory, peripheral, or USB capability variants without PCB changes in the LPC11E67JBD64E platform.
LPC11E67JBD64E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 64-LQFP
- Series:
- LPC11Exx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, Microwire, SPI, SSI, SSP, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 50
- Program Memory Size:
- 128KB (128K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 20K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 10x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC11E67JBD64E FAQ
1.How can I place an order for LPC11E67JBD64E through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC11E67JBD64E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC11E67JBD64E reliable?
The price and inventory of LPC11E67JBD64E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC11E67JBD64E is usually 5 days.
3.What payment methods are accepted for LPC11E67JBD64E?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC11E67JBD64E transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC11E67JBD64E?
LPC11E67JBD64E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC11E67JBD64E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC11E67JBD64E?
For technical support, including LPC11E67JBD64E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC11E67JBD64E requirements.
6.How does Aetrix verify that LPC11E67JBD64E is sourced from the original manufacturer or authorized distributors?
All LPC11E67JBD64E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC11E67JBD64E meets industry standards.
7.What is the process for return or replacement of LPC11E67JBD64E?
All LPC11E67JBD64E units undergo pre-shipment inspection (PSI). If there is an issue with LPC11E67JBD64E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC11E67JBD64E part is unused and in its original packaging.
Return procedure for LPC11E67JBD64E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC11E67JBD64E Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

