NXP Semiconductors LPC11E68JBD64E
- Part No.:
- LPC11E68JBD64E
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 64-LQFP
- Datasheet:
-
LPC11E68JBD64E.pdf
- Description:
- IC MCU 32BIT 256KB FLASH 64LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
LPC11E68JBD64E from NXP Semiconductors is a 32-bit ARM Cortex-M0+ microcontroller operating at up to 50 MHz, featuring 256 KB flash, 36 KB SRAM, 4 KB EEPROM, a 12-bit ADC with 10 input channels, and 50 GPIO pins. It integrates dual I²C (one Fast-mode Plus), five USARTs (four with shared fractional baud generator), two SSP interfaces, SCTimer/PWM subsystem, RTC with VBAT support, and operates across −40 °C to +105 °C for industrial metering and embedded control.
For engineers reviewing the LPC11E68JBD64E datasheet, LPC11E68JBD64E pinout, LPC11E68JBD64E application, or LPC11E68JBD64E equivalent, key selection criteria include its LQFP64 package with 50 GPIO, 10-channel 12-bit ADC sampling up to 2 Msamples/s, dual I²C with Fast-mode Plus capability, and support for Deep power-down wake-up via PIO0_16 - critical for low-power sensor nodes and portable medical monitors.
Technical Context
The LPC11E68JBD64E implements an ARM Cortex-M0+ core (r0p1) with a two-stage pipeline, single-cycle I/O, and integrated NVIC for deterministic interrupt handling. Its AHB multilayer matrix enables concurrent peripheral access without bus contention, while the ROM API provides validated drivers for USART, I²C, DMA, and Flash IAP/ISP - reducing firmware development time for certified firmware updates.
Its analog subsystem centers on a 12-bit ADC supporting two independent conversion sequences, internal/external triggers, and up to 2 Msamples/s throughput. The configurable SCTimer/PWM subsystem delivers up to 19 PWM outputs with six independent time bases, enabling precise motor control or LED dimming in resource-constrained designs.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0+ (r0p1), 50 MHz max - enables real-time deterministic response with <10 ns I/O latency and low power consumption vs Cortex-M3/M4. |
| Memory | 256 KB flash (page-erasable), 36 KB SRAM (32 KB main + two 2 KB blocks), 4 KB EEPROM - supports field firmware updates and non-volatile parameter storage without external components. |
| ADC | 12-bit resolution, 10 input channels, 2 Msamples/s max - sufficient for high-fidelity sensor acquisition in e-meters and medical monitors. |
| Serial Interfaces | 5 USARTs (4 with shared fractional baud generator), 2 I²C (1 Fast-mode Plus), 2 SSP - enables simultaneous RS-485 communication, I²C sensor hub, and SPI display interface. |
| Timers & PWM | SCTimer/PWM subsystem with 19 PWM outputs, 6 independent time bases; plus four standard timers (two 16-bit, two 32-bit) - supports multi-phase motor control or synchronized lighting systems. |
| Power & Temp | 2.4–3.6 V supply, −40 °C to +105 °C operation, Deep power-down mode with PIO0_16 wake-up - suitable for automotive cabin modules and industrial edge controllers. |
| Package | LQFP64 (10 × 10 × 1.4 mm, SOT314-2) with 50 GPIO - balances PCB density and debug/test accessibility for mid-complexity embedded applications. |
Pinout & Package
LQFP64 package (SOT314-2), 10 × 10 × 1.4 mm body, 64-pin quad flat lead frame with exposed thermal pad (not electrically connected). Pin 1 index marked by corner notch; pins numbered counterclockwise.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (RTCXIN) | RTC oscillator input | Accepts 32.768 kHz crystal for battery-backed real-time clock; requires external load capacitors. |
| 2 (RTCXOUT) | RTC oscillator output | Drives 32.768 kHz crystal; must be used with RTCXIN for autonomous RTC operation during VDD loss. |
| 4 (RESET/PIO0_0) | Reset input / GPIO | Active-low reset with 20 ns glitch filter; doubles as SWD debug select (HIGH = SWD, LOW = JTAG). |
| 28 (SWCLK/PIO0_10) | SWD clock / GPIO | Default Serial Wire Debug clock; configurable as general-purpose I/O after debug initialization. |
| 39 (SWDIO/PIO0_15) | SWD bidirectional I/O / GPIO | Primary debug data line; supports SWD protocol and full GPIO functionality with pull-up/pull-down control. |
| 51 (PIO0_16/WAKEUP) | GPIO / Deep power-down wake-up | Dual-role pin: general-purpose I/O with programmable filter; LOW pulse ≥50 ns wakes device from Deep power-down mode. |
| 53 (VDDA) | Analog power supply | Separate 2.4–3.6 V supply for ADC and analog peripherals; must be filtered independently from digital VDD. |
| 54 (VSSA) | Analog ground | Dedicated analog return path; requires star grounding near VDDA to minimize ADC noise. |
| 63 (VBAT) | RTC backup supply | Connects to coin cell or supercapacitor to maintain RTC and backup registers during main power loss. |
Key Features
| Feature | Design Value |
|---|---|
| ROM-based USB-free ISP/IAP | Enables firmware updates over UART or I²C without external programmer - critical for deployed medical devices requiring regulatory-compliant field upgrades. |
| Micro Trace Buffer (MTB) | Provides hardware-assisted instruction trace in SRAM for debugging real-time behavior without JTAG bandwidth overhead. |
| Configurable glitch filter on GPIO | Programmable digital filter per pin (up to 100 ns) suppresses EMI-induced false interrupts in noisy industrial environments. |
| Windowed Watchdog Timer (WWDT) | Prevents runaway code by requiring periodic windowed refresh - mandatory for safety-critical functions like car radio power management. |
| Temperature sensor | On-die sensor calibrated to ±5 °C accuracy enables thermal derating and ambient compensation in GPS trackers and gaming accessories. |
| High-speed GPIO with 80-pin capability | Direct AHB bus connection enables sub-cycle I/O toggling - essential for bit-banged protocols or precise timing-critical signal generation. |
Applications
| Three-Phase E-Meter | Medical Monitor |
|---|---|
Use Scenario: High-accuracy energy measurement in utility-grade smart meters with anti-tampering features and secure firmware updates. IC Role / Device Role / Timing Role: Main system controller executing metrology algorithms, managing isolated RS-485 communication, and storing calibration data in EEPROM. Use Value: 12-bit ADC with 10 channels and 2 Msamples/s supports simultaneous voltage/current sampling; 256 KB flash hosts dual-bank firmware for fail-safe OTA updates. |
Use Scenario: Portable patient vital sign monitor requiring long battery life, clinical-grade sensor interfacing, and regulatory-compliant data logging. IC Role / Device Role / Timing Role: Central MCU handling ECG/SpO₂ sensor acquisition, LCD display control, Bluetooth LE interface, and RTC-stamped data storage. Use Value: Deep power-down mode with PIO0_16 wake-up extends battery life; VBAT-supplied RTC maintains timestamp integrity during power cycling. |
| GPS Tracker | Car Radio |
Use Scenario: Compact vehicle telematics unit with GNSS receiver, cellular modem, and motion-triggered wake-up for fleet management. IC Role / Device Role / Timing Role: Host processor managing GNSS UART parsing, accelerometer interrupt handling, and modem command sequencing. Use Value: Five USARTs enable concurrent GNSS NMEA, modem AT commands, and CAN diagnostics; temperature sensor enables thermal compensation of GNSS timing drift. |
Use Scenario: Automotive infotainment head unit subsystem controlling display backlight, audio DAC, touch panel, and steering wheel controls. IC Role / Device Role / Timing Role: Secondary MCU offloading UI responsiveness, button debouncing, and RGB LED dimming from main SoC. Use Value: SCTimer/PWM with 19 outputs drives multi-zone LED backlighting; -40 °C to +105 °C rating ensures reliability in dashboard thermal environments. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC11U68JBD64E | Same core/peripherals but adds USB 2.0 device controller and enhanced ROM API; 256 KB flash, 36 KB SRAM, same LQFP64 package. | Required where USB HID or CDC-class connectivity is needed (e.g., PC peripherals, diagnostic tools); not suitable if USB adds unnecessary BOM cost or EMI risk. | Select LPC11U68JBD64E only when native USB device functionality is mandatory; otherwise LPC11E68JBD64E offers lower system complexity and reduced EMC filtering burden. |
| STM32F072RBT6 | ARM Cortex-M0, 48 MHz, 128 KB flash, 16 KB SRAM, 12-bit ADC (16 ch), USB 2.0, LQFP64 - lacks EEPROM and Fast-mode Plus I²C. | Better suited for USB-centric designs (e.g., HID keyboards) but requires external EEPROM for parameter storage and cannot drive legacy Fast-mode Plus I²C sensors directly. | Choose STM32F072RBT6 when USB host/device capability is primary; LPC11E68JBD64E remains superior for I²C sensor hubs, e-metering, or applications needing on-chip EEPROM and extended temp range. |
Compared with LPC11U68JBD64E, the LPC11E68JBD64E reduces design complexity by omitting USB PHY and associated layout constraints, while retaining identical analog performance and industrial temperature support; versus STM32F072RBT6, it provides integrated EEPROM and Fast-mode Plus I²C - eliminating external components and enabling direct interface with high-speed I²C sensors.
Availability
LPC11E68JBD64E is available at Aetrix Electronics and suitable for three-phase e-metering, portable medical monitoring, and automotive infotainment subsystems requiring stable component supply, long-term industrial lifecycle support, and guaranteed availability through 2030.
Supply support for LPC11E68JBD64E includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with headquarters in Eindhoven, Netherlands.
The LPC11E6x family was designed for cost-sensitive, low-power embedded control applications demanding robust analog integration, field-upgradable firmware, and extended temperature operation - targeting smart energy, medical wearables, and automotive body electronics.
FAQ
What is the maximum ADC sampling rate supported by the LPC11E68JBD64E?
The LPC11E68JBD64E supports a maximum ADC sampling rate of 2 Msamples/s. This throughput is achievable using internal triggers and optimized sequence configuration. The 12-bit ADC includes two independent conversion sequences and supports multiple trigger sources including timers and external pins - enabling synchronized sampling across up to 10 channels for applications like three-phase e-metering where phase-aligned voltage and current measurements are critical.
Does the LPC11E68JBD64E support USB device functionality?
No, the LPC11E68JBD64E does not include a USB controller. It belongs to the LPC11E6x series, which focuses on UART, I²C, and SPI connectivity. For USB-capable variants in the same footprint and feature set, consider the LPC11U68JBD64E - a pin-compatible alternative with integrated USB 2.0 device controller and enhanced ROM API, though it lacks the same level of analog peripheral optimization as the LPC11E68JBD64E.
How many USART interfaces does the LPC11E68JBD64E provide, and what are their key capabilities?
The LPC11E68JBD64E provides five USART interfaces. Four support a shared fractional baud rate generator and RS-485 mode; all five include DMA support and synchronous operation. USART0–3 are available in the LQFP64 package, while USART4 is exclusive to LQFP100. This enables concurrent communication with GNSS modules (UART), cellular modems (RS-485), and diagnostic interfaces (synchronous SPI-like mode) - ideal for GPS trackers and industrial gateways.
What power modes are available on the LPC11E68JBD64E, and how is wake-up implemented from Deep power-down?
The LPC11E68JBD64E supports Sleep, Deep-sleep, Power-down, and Deep power-down modes. Wake-up from Deep power-down is implemented exclusively via PIO0_16: a LOW-going pulse ≥50 ns on this pin exits the mode. External pull-up is required before entry, and the pin must be driven LOW to initiate wake-up. This hardware-level mechanism ensures ultra-low leakage (<1 µA) and deterministic recovery - essential for battery-powered medical monitors and environmental sensors.
Is the LPC11E68JBD64E pin-compatible with other members of the LPC11E6x family?
Yes, the LPC11E68JBD64E shares the same LQFP64 (SOT314-2) package and pinout with LPC11E67JBD64 and LPC11E66JBD64. Differences lie in memory size (256 KB vs 128 KB vs 64 KB flash) and peripheral enablement (e.g., USART4 is disabled in all LQFP64 variants). This allows scalable firmware deployment and BOM optimization - for example, using LPC11E68JBD64E for feature-rich versions and downgrading flash-only in cost-sensitive SKUs without PCB redesign.
LPC11E68JBD64E Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 64-LQFP
- Series:
- LPC11Exx
- Packaging:
- Tray
- Product Status:
- Discontinued at Digi-Key
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0+
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, Microwire, SPI, SSI, SSP, UART/USART
- Peripherals:
- Brown-out Detect/Reset, DMA, POR, PWM, WDT
- Number of I/O:
- 50
- Program Memory Size:
- 256KB (256K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 4K x 8
- RAM Size:
- 36K x 8
- Voltage - Supply (Vcc/Vdd):
- 2.4V ~ 3.6V
- Data Converters:
- A/D 10x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC11E68JBD64E FAQ
1.How can I place an order for LPC11E68JBD64E through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC11E68JBD64E on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC11E68JBD64E reliable?
The price and inventory of LPC11E68JBD64E are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC11E68JBD64E is usually 5 days.
3.What payment methods are accepted for LPC11E68JBD64E?
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4.How is shipping managed for LPC11E68JBD64E?
LPC11E68JBD64E orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC11E68JBD64E order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC11E68JBD64E?
For technical support, including LPC11E68JBD64E datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC11E68JBD64E requirements.
6.How does Aetrix verify that LPC11E68JBD64E is sourced from the original manufacturer or authorized distributors?
All LPC11E68JBD64E products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC11E68JBD64E meets industry standards.
7.What is the process for return or replacement of LPC11E68JBD64E?
All LPC11E68JBD64E units undergo pre-shipment inspection (PSI). If there is an issue with LPC11E68JBD64E, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC11E68JBD64E part is unused and in its original packaging.
Return procedure for LPC11E68JBD64E:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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