NXP Semiconductors LPC11U23FBD48/301,
- Part No.:
- LPC11U23FBD48/301,
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 48-LQFP
- Datasheet:
-
LPC11U23FBD48/301,.pdf
- Description:
- IC MCU 32BIT 24KB FLASH 48LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:146
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
LPC11U23FBD48/301 from NXP Semiconductors is a 32-bit ARM Cortex-M0 microcontroller in LQFP48 package, operating up to 50 MHz with 24 kB flash, 6 kB SRAM, and 1 kB EEPROM. It integrates Full-Speed USB 2.0 device controller, 10-bit ADC (8-channel), two SSP interfaces, I²C-bus (Fast-mode Plus), and USART with RS-485/smart card support - enabling compact, low-power USB-connected embedded control in medical peripherals and industrial gateways.
For engineers reviewing the LPC11U23FBD48/301 datasheet, LPC11U23FBD48/301 pinout, LPC11U23FBD48/301 application, or LPC11U23FBD48/301 equivalent, key selection criteria include USB device stack readiness, on-chip EEPROM for configuration storage, 40 GPIO with interrupt grouping, and support for deep power-down wake-up via dedicated WAKEUP pin - all within a 7×7 mm LQFP48 footprint.
Technical Context
The LPC11U23FBD48/301 implements a single-core ARM Cortex-M0 CPU with NVIC and system tick timer, paired with dual PLLs - one for CPU clocking (up to 50 MHz) and a dedicated USB PLL for precise 48 MHz timing. Its memory subsystem includes boot ROM with USB drivers and integer division routines, enabling firmware updates over USB without external host software.
Digital peripheral routing is managed through configurable IOCON registers per pin, supporting pull-up/pull-down, repeater, and open-drain modes. Analog functions (ADC inputs AD0–AD7) disable digital circuitry when active, ensuring signal integrity; true open-drain I²C pins (PIO0_4/SCL, PIO0_5/SDA) support Fast-mode Plus (1 Mbit/s) with external pull-ups.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | ARM Cortex-M0, 32-bit RISC, supports Thumb-2 instruction set for compact code size vs. 8/16-bit MCUs. |
| Max Clock Frequency | 50 MHz - achieved via PLL using internal 12 MHz IRC or external crystal (1–25 MHz), enabling real-time USB frame handling. |
| Memory | 24 kB flash (in-system programmable), 6 kB SRAM, 1 kB EEPROM (byte-erasable), 16 kB boot ROM with USB API and power profiles. |
| USB Interface | Full-Speed USB 2.0 device controller with dedicated PLL, VBUS detection, SoftConnect, and ROM-based drivers - eliminates need for external USB PHY or firmware stack. |
| Analog Peripherals | 10-bit ADC with 8 input channels (AD0–AD7), sampled at up to 400 kS/s; no internal reference - uses VDD as reference voltage. |
| Digital I/O | 40 GPIO pins in LQFP48 package, with 8 configurable as edge/level-sensitive interrupts and two GPIO group interrupt modules for pattern-matching wake-up. |
| Power Management | Four low-power modes (Sleep, Deep-sleep, Power-down, Deep power-down); wake-up from Deep power-down via dedicated PIO0_16/WAKEUP pin with 20 ns glitch filter. |
Pinout & Package
LQFP48 package: plastic low-profile quad flat package, 48 leads, body size 7 × 7 × 1.4 mm (SOT313-2). Pin pitch: 0.5 mm. RoHS-compliant, lead-free finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RESET/PIO0_0 | Reset input / GPIO | Active-low reset with 20 ns glitch filter; also debug select pin (LOW = JTAG, HIGH = SWD); must be pulled HIGH externally in Deep power-down mode. |
| USB_DP / USB_DM | USB differential data pair | Full-Speed USB 2.0 D+ and D− lines compliant with USB spec rev 2.0; not 5 V tolerant; require 1.5 kΩ pull-up on DP for device enumeration. |
| PIO0_16/AD5/CT32B1_MAT3/WAKEUP | Multi-function pin | In Deep power-down mode, functions exclusively as WAKEUP input with 50 ns pulse detection; also serves as ADC input 5 and match output 3 for 32-bit timer 1. |
| PIO0_4/SCL & PIO0_5/SDA | I²C-bus interface | Open-drain pins supporting Fast-mode Plus (1 Mbit/s); high-current sink only when Fast-mode Plus enabled in IOCON; require external pull-ups. |
| VDD / VSS | Power supply | Single 3.3 V supply (1.8–3.6 V range); VDD also serves as ADC reference voltage; two VDD and two VSS pins in LQFP48 for noise reduction. |
Key Features
| Feature | Design Value |
|---|---|
| ROM-based USB device stack | Eliminates external USB PHY and reduces firmware development time - enables plug-and-play USB audio or HID functionality with minimal code. |
| Byte-programmable EEPROM | 1 kB on-chip EEPROM allows field-updatable calibration data, serial numbers, or user settings without flash wear leveling overhead. |
| Configurable GPIO interrupt groups | Two GPIO group interrupt modules detect programmable logic patterns across multiple pins - ideal for keypad scan or multi-sensor event triggering. |
| Dedicated Deep power-down wake-up pin | PIO0_16/WAKEUP provides deterministic, ultra-low-power wake-up (<1 µA retention current) with hardware-debounced 50 ns pulse detection. |
| USART with smart card interface | Supports ISO/IEC 7816-3 asynchronous smart card protocol and RS-485 half-duplex mode - enables secure access control or industrial bus node design. |
Applications
| USB Audio Peripheral | Industrial RS-485 Gateway |
|---|---|
Use Scenario: Compact USB-powered headset controller with analog mic input and LED status feedback. IC Role / Device Role / Timing Role: Main MCU executing USB audio class (UAC1) firmware, sampling mic via 10-bit ADC, driving GPIO LEDs, and managing USB enumeration via SoftConnect. Use Value: ROM-based USB drivers reduce BOM cost and firmware size; 1 kB EEPROM stores device-specific vendor descriptors and volume calibration. |
Use Scenario: DIN-rail mounted converter bridging Modbus RTU (RS-485) to USB-CDC for PC-based SCADA systems. IC Role / Device Role / Timing Role: Protocol translator with USART in RS-485 mode (9-bit address detection), USB CDC ACM class interface, and GPIO-controlled direction control. Use Value: Dual SSP interfaces allow isolated SPI communication with external isolators; 40 GPIO enable status LED banks and fault signaling without external logic. |
| Handheld Medical Scanner | Low-Power Smart Sensor Node |
Use Scenario: Battery-operated barcode scanner with laser trigger, decode engine, and USB mass-storage emulation for firmware updates. IC Role / Device Role / Timing Role: Real-time decoder host with USB MSC class, 50 MHz CPU for fast image processing, and wake-up from Deep power-down on button press. Use Value: Dedicated WAKEUP pin (PIO0_16) enables sub-µA sleep current; 24 kB flash accommodates both application and bootloader with IAP support. |
Use Scenario: Wireless sensor node collecting temperature/humidity via I²C sensors, logging to EEPROM, and uploading via USB when docked. IC Role / Device Role / Timing Role: Data concentrator with I²C Fast-mode Plus (1 Mbit/s) for fast sensor reads, 1 kB EEPROM for local history, and USB for bulk transfer. Use Value: I²C pins support 1 Mbit/s with hardware filtering; low-power modes extend battery life; ROM power profiles simplify sleep/wake configuration. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| LPC11U24FBD48/301 | 32 kB flash, 2 kB EEPROM, 6 kB SRAM - +8 kB flash and +1 kB EEPROM vs. LPC11U23FBD48/301; identical pinout and peripherals. | Required for larger USB firmware images or extended EEPROM logging; same LQFP48 footprint and migration path. | Select when firmware exceeds 24 kB or EEPROM usage exceeds 1 kB - drop-in replacement with no layout change. |
| STM32F042F4P6 | ARM Cortex-M0, 16 kB flash, 6 kB SRAM, USB 2.0 FS, but no on-chip EEPROM; requires external EEPROM or flash emulation. | Suitable for cost-sensitive USB HID designs where EEPROM is unnecessary; lacks native EEPROM and Fast-mode Plus I²C. | Choose if USB HID/CDC is primary function and EEPROM is not required - verify I²C speed and power profile needs separately. |
Compared with LPC11U24FBD48/301, the LPC11U23FBD48/301 trades flash and EEPROM capacity for tighter BOM cost control while retaining full USB device capability and low-power features; versus STM32F042F4P6, it offers integrated EEPROM and higher I²C speed but with NXP toolchain dependency.
Availability
LPC11U23FBD48/301 is available at Aetrix Electronics and suitable for USB-connected medical peripherals, industrial gateways, and handheld scanners requiring stable component supply, long-term lifecycle assurance, and RoHS-compliant LQFP packaging.
Supply support for LPC11U23FBD48/301 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.
The LPC11U2x product line was designed specifically for cost-sensitive, USB-enabled 32-bit embedded applications - delivering Cortex-M0 performance with integrated USB device stack, EEPROM, and ultra-low-power operation in small-footprint packages.
FAQ
What is the maximum operating frequency of the LPC11U23FBD48/301?
The LPC11U23FBD48/301 operates at a maximum CPU frequency of 50 MHz. This is achieved using either the internal 12 MHz IRC oscillator or an external crystal (1–25 MHz) fed into a dedicated PLL. The USB subsystem uses a separate PLL locked to 48 MHz for Full-Speed compliance, independent of CPU clock scaling.
Does the LPC11U23FBD48/301 include on-chip EEPROM, and what are its programming characteristics?
Yes, the LPC11U23FBD48/301 includes 1 kB of on-chip EEPROM that is byte-erasable and byte-programmable. It is accessed via In-Application Programming (IAP) calls from the boot ROM, eliminating the need for external EEPROM or flash wear-leveling algorithms. Write endurance is rated at 100,000 cycles per byte.
How does the USB interface of the LPC11U23FBD48/301 differ from standard USB-capable MCUs?
The LPC11U23FBD48/301 integrates a Full-Speed USB 2.0 device controller with ROM-based drivers supporting USB CDC, HID, and MSC classes. Unlike many MCUs requiring external PHY or stack licensing, it includes SoftConnect (software-controlled 1.5 kΩ pull-up), VBUS sensing, and enumeration firmware - enabling USB functionality with zero external components beyond passive termination.
Which pins on the LPC11U23FBD48/301 support analog-to-digital conversion?
The LPC11U23FBD48/301 supports eight ADC input channels mapped to specific GPIO pins: AD0 (PIO0_11), AD1 (PIO0_12), AD2 (PIO0_13), AD3 (PIO0_14), AD4 (PIO0_15), AD5 (PIO0_16), AD6 (PIO0_22), and AD7 (PIO0_23). When configured as ADC inputs, the digital section of each pin is disabled, and the pin is no longer 5 V tolerant.
What power-saving modes are supported by the LPC11U23FBD48/301, and how is wake-up implemented from Deep power-down?
The LPC11U23FBD48/301 supports four power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. From Deep power-down (sub-1 µA), wake-up is possible only via the dedicated PIO0_16/WAKEUP pin, which detects a LOW-going pulse as short as 50 ns. External pull-up is required on this pin during Deep power-down operation.
LPC11U23FBD48/301, Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 48-LQFP
- Series:
- LPC11Uxx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- ARM® Cortex®-M0
- Core Size:
- 32-Bit Single-Core
- Speed:
- 50MHz
- Connectivity:
- I2C, Microwire, SPI, SSI, SSP, UART/USART, USB
- Peripherals:
- Brown-out Detect/Reset, POR, WDT
- Number of I/O:
- 40
- Program Memory Size:
- 24KB (24K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 1K x 8
- RAM Size:
- 8K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.8V ~ 3.6V
- Data Converters:
- A/D 8x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
LPC11U23FBD48/301, FAQ
1.How can I place an order for LPC11U23FBD48/301, through Aetrix?
Please submit a Request for Quotation (RFQ) for LPC11U23FBD48/301, on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for LPC11U23FBD48/301, reliable?
The price and inventory of LPC11U23FBD48/301, are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for LPC11U23FBD48/301, is usually 5 days.
3.What payment methods are accepted for LPC11U23FBD48/301,?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for LPC11U23FBD48/301, transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for LPC11U23FBD48/301,?
LPC11U23FBD48/301, orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your LPC11U23FBD48/301, order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for LPC11U23FBD48/301,?
For technical support, including LPC11U23FBD48/301, datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your LPC11U23FBD48/301, requirements.
6.How does Aetrix verify that LPC11U23FBD48/301, is sourced from the original manufacturer or authorized distributors?
All LPC11U23FBD48/301, products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that LPC11U23FBD48/301, meets industry standards.
7.What is the process for return or replacement of LPC11U23FBD48/301,?
All LPC11U23FBD48/301, units undergo pre-shipment inspection (PSI). If there is an issue with LPC11U23FBD48/301,, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The LPC11U23FBD48/301, part is unused and in its original packaging.
Return procedure for LPC11U23FBD48/301,:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
LPC11U23FBD48/301, Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

