NXP Semiconductors LPC11U35FHI33/501,

Overview

LPC11U35FHI33/501 from NXP Semiconductors is a 32-bit ARM Cortex-M0 microcontroller in a 33-terminal HVQFN package (5 × 5 × 0.85 mm), operating up to 50 MHz with 64 kB flash, 12 kB SRAM (including 2 kB USB SRAM), and 4 kB EEPROM. It integrates USB 2.0 full-speed device controller, USART with RS-485/smart card support, I²C-bus (Fast-mode Plus), two SSP interfaces, 10-bit ADC (8 channels), and up to 26 GPIO pins - deployed in USB audio devices and handheld scanners requiring compact, low-power connectivity.

For engineers reviewing the LPC11U35FHI33/501 datasheet, LPC11U35FHI33/501 pinout, LPC11U35FHI33/501 application, or LPC11U35FHI33/501 equivalent, key selection criteria include its HVQFN33 footprint, USB device stack support in ROM, 12 kB total SRAM allocation (8 kB + 2 kB USB + 2 kB general-purpose), 4 kB byte-erasable EEPROM, and absence of I/O Handler hardware - distinguishing it from LPC11U37HFBD64/401.

Technical Context

The LPC11U35FHI33/501 implements an ARM Cortex-M0 core with NVIC and system tick timer, paired with a dedicated USB PLL and main PLL for clock generation. Its memory subsystem includes 64 kB flash (sector/page erase), 4 kB EEPROM (byte-programmable with on-chip API), and 12 kB SRAM split across general-purpose (8 kB), USB (2 kB), and additional general-purpose (2 kB) banks.

Digital peripherals include one USART supporting asynchronous/synchronous modes and ISO 7816-3 smart card interface, two SSP controllers with FIFOs, Fast-mode Plus I²C-bus (1 Mbit/s), four timers (two 32-bit, two 16-bit), and a 10-bit ADC with eight input channels. Power management supports Sleep, Deep-sleep, Power-down, and Deep power-down modes with wake-up via GPIO, watchdog, or USB activity.

Key Specifications

Pinout & Package

Package: HVQFN33 (plastic thermal enhanced very thin quad flat package; no leads; 33 terminals; body 5 × 5 × 0.85 mm).

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar microcontroller applications.

Compared with LPC11U35FHN33/401, the LPC11U35FHI33/501 adds 2 kB of general-purpose SRAM and reduces package area by 49 %; versus LPC11U35FET48/501, it trades 14 GPIO pins and BGA complexity for superior manufacturability in space-constrained USB peripherals.

Availability

LPC11U35FHI33/501 is available at Aetrix Electronics and suitable for USB audio devices, handheld scanners, and medical sensors requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.

Supply support for LPC11U35FHI33/501 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

NXP Semiconductors is a global semiconductor company headquartered in Eindhoven, Netherlands, specializing in secure connectivity solutions for automotive, industrial, and IoT markets.

The LPC11U3x product line targets cost-sensitive, USB-connected embedded applications where low power, small footprint, and integrated USB device functionality are critical - exemplified by the LPC11U35FHI33/501's HVQFN33 form factor and ROM-based USB stack.

FAQ

What is the maximum operating frequency of the LPC11U35FHI33/501?

The LPC11U35FHI33/501 operates at a maximum CPU frequency of 50 MHz, achieved using either the internal 12 MHz IRC oscillator with PLL multiplication or an external crystal (1–25 MHz) fed into the system oscillator and scaled via PLL. This frequency is confirmed in Section 1 and Table 2 of the official NXP datasheet Rev. 2.5.

Does the LPC11U35FHI33/501 include an I/O Handler peripheral?

No, the LPC11U35FHI33/501 does not include the I/O Handler hardware block. According to Table 2 in the datasheet, I/O Handler is only present in the LPC11U37HFBD64/401 variant. The LPC11U35FHI33/501 relies on standard GPIO and peripheral controllers for serial interface implementation.

What is the exact SRAM configuration of the LPC11U35FHI33/501?

The LPC11U35FHI33/501 has 12 kB of total SRAM: 8 kB general-purpose SRAM (SRAM0), 2 kB dedicated USB SRAM, and 2 kB additional general-purpose SRAM (SRAM1). This allocation is explicitly defined in Table 2 under "Total SRAM in kB [1]" and footnoted as "[1] For general-purpose use."

Which package dimensions does the LPC11U35FHI33/501 use?

The LPC11U35FHI33/501 uses the HVQFN33 package with physical dimensions of 5 mm × 5 mm × 0.85 mm, distinct from the larger 7 mm × 7 mm HVQFN33 variants (e.g., LPC11U35FHN33/401). This information is specified in the Ordering Information table (Section 4) of the datasheet.

Can the LPC11U35FHI33/501 perform in-system programming (ISP) via USB?

Yes, the LPC11U35FHI33/501 supports flash updates via USB using its ROM-based bootloader and integrated USB device controller. Section 2 confirms "Flash updates via USB supported," and Section 6.2 notes that a HIGH level on PIO0_3/USB_VBUS during reset initiates USB device enumeration - enabling direct firmware upload without UART or debugger hardware.